riscv: dts: sophgo: cv18xx: add DMA controller

Add DMA controller dt node for CV18XX/SG200x.

Link: https://lore.kernel.org/r/IA1PR20MB4953BD73E12B8A1CDBD9E1A3BB042@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index 891932ae470f3421ee6a9c0ee2660603f9904c69..b724fb6d9689ef65cfe9470a1f614df30e4ca147 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -297,6 +297,22 @@
                        status = "disabled";
                };
 
+               dmac: dma-controller@4330000 {
+                       compatible = "snps,axi-dma-1.01a";
+                       reg = <0x04330000 0x1000>;
+                       interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
+                       clock-names = "core-clk", "cfgr-clk";
+                       #dma-cells = <1>;
+                       dma-channels = <8>;
+                       snps,block-size = <1024 1024 1024 1024
+                                          1024 1024 1024 1024>;
+                       snps,priority = <0 1 2 3 4 5 6 7>;
+                       snps,dma-masters = <2>;
+                       snps,data-width = <4>;
+                       status = "disabled";
+               };
+
                plic: interrupt-controller@70000000 {
                        reg = <0x70000000 0x4000000>;
                        interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;