if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
                highbank_scu_map_io();
-
-       /* Enable PL310 L2 Cache controller */
-       if (IS_ENABLED(CONFIG_CACHE_L2X0)) {
-               outer_cache.write_sec = highbank_l2c310_write_sec;
-               l2x0_of_init(0, ~0);
-       }
 }
 
 static void highbank_power_off(void)
 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
        .dma_zone_size  = (4ULL * SZ_1G),
 #endif
+       .l2c_aux_val    = 0,
+       .l2c_aux_mask   = ~0,
+       .l2c_write_sec  = highbank_l2c310_write_sec,
        .init_irq       = highbank_init_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,