drm/amd/powerplay: add funciton force_dpm_limit for navi10

add callback function force_dpm_limit for navi10 asic

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index bcd2adca6ed7bdf34ca6f32889c11061b224c1b8..6f05816842ce8a3e34149a277bfe1b9b7c1dbeea 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -695,6 +695,34 @@ static int navi10_display_config_changed(struct smu_context *smu)
 
        return ret;
 }
+
+static int navi10_force_dpm_limit_value(struct smu_context *smu, bool highest)
+{
+       int ret = 0, i = 0;
+       uint32_t min_freq, max_freq, force_freq;
+       enum smu_clk_type clk_type;
+
+       enum smu_clk_type clks[] = {
+               SMU_GFXCLK,
+               SMU_MCLK,
+               SMU_SOCCLK,
+       };
+
+       for (i = 0; i < ARRAY_SIZE(clks); i++) {
+               clk_type = clks[i];
+               ret = smu_get_dpm_freq_range(smu, clk_type, &min_freq, &max_freq);
+               if (ret)
+                       return ret;
+
+               force_freq = highest ? max_freq : min_freq;
+               ret = smu_set_soft_freq_range(smu, clk_type, force_freq, force_freq);
+               if (ret)
+                       return ret;
+       }
+
+       return ret;
+}
+
 static const struct pptable_funcs navi10_ppt_funcs = {
        .tables_init = navi10_tables_init,
        .alloc_dpm_context = navi10_allocate_dpm_context,
@@ -716,6 +744,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
        .pre_display_config_changed = navi10_pre_display_config_changed,
        .display_config_changed = navi10_display_config_changed,
+       .force_dpm_limit_value = navi10_force_dpm_limit_value,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)