drm_kms_helper_hotplug_event(dev);
 }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 /* Allocate memory for FBC compressed data  */
 static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 {
        }
 
 }
-#endif
 
 
 /* Init display KMS
        amdgpu_dm_connector_ddc_get_modes(connector, edid);
        amdgpu_dm_connector_add_common_modes(encoder, connector);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        amdgpu_dm_fbc_init(connector);
-#endif
+
        return amdgpu_dm_connector->num_modes;
 }
 
 
 #include "dce/dce_hwseq.h"
 #include "gpio_service_interface.h"
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
 #include "dce110_compressor.h"
-#endif
 
 #include "bios/bios_parser_helper.h"
 #include "timing_generator.h"
 
        power_down_clock_sources(dc);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-#endif
 }
 
 static void disable_vga_and_power_gate_all_controllers(
        if (events->force_trigger)
                value |= 0x1;
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        value |= 0x84;
-#endif
 
        for (i = 0; i < num_pipes; i++)
                pipe_ctx[i]->stream_res.tg->funcs->
        }
 }
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
-
 /*
  *  Check if FBC can be enabled
  */
                compr->funcs->enable_fbc(compr, ¶ms);
        }
 }
-#endif
 
 static void dce110_reset_hw_ctx_wrap(
                struct dc *dc,
 
        set_safe_displaymarks(&context->res_ctx, dc->res_pool);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
-#endif
+
        /*TODO: when pplib works*/
        apply_min_clocks(dc, context, &clocks_state, true);
 
 
        dcb->funcs->set_scratch_critical_state(dcb, false);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        if (dc->fbc_compressor)
                enable_fbc(dc, context);
 
-#endif
-
        return DC_OK;
 }
 
                abm->funcs->init_backlight(abm);
                abm->funcs->abm_init(abm);
        }
-#if defined(CONFIG_DRM_AMD_DC_FBC)
+
        if (dc->fbc_compressor)
                dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
-#endif
 
 }
 
        struct dc_plane_state *plane_state = pipe_ctx->plane_state;
        struct xfm_grph_csc_adjustment adjust;
        struct out_csc_color_matrix tbl_entry;
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
-#endif
        unsigned int i;
        DC_LOGGER_INIT();
        memset(&tbl_entry, 0, sizeof(tbl_entry));
 
        program_scaler(dc, pipe_ctx);
 
-#if defined(CONFIG_DRM_AMD_DC_FBC)
        /* fbc not applicable on Underlay pipe */
        if (dc->fbc_compressor && old_pipe->stream &&
            pipe_ctx->pipe_idx != underlay_idx) {
                else
                        enable_fbc(dc, dc->current_state);
        }
-#endif
 
        mi->funcs->mem_input_program_surface_config(
                        mi,