return ret;
 
        clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]);
-       if (!clk_rate)
-               return -EINVAL;
+       if (!clk_rate) {
+               ret = -EINVAL;
+               goto out;
+       }
 
        /* Make sure we use the bus clock and not the 26MHz clock */
        if (pc->soc->has_ck_26m_sel)
        }
 
        if (clkdiv > PWM_CLK_DIV_MAX) {
-               pwm_mediatek_clk_disable(chip, pwm);
                dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns);
-               return -EINVAL;
+               ret = -EINVAL;
+               goto out;
        }
 
        if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) {
        pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period);
        pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty);
 
+out:
        pwm_mediatek_clk_disable(chip, pwm);
 
-       return 0;
+       return ret;
 }
 
 static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm)