drm/i915/pvc: Interrupt support for new copy engines

Add the interrupt handler support for new copy engines.

Bspec: 54030
Original-author: CQ Tang
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-10-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 88b4becfcb175b11d2813f1685ffbf83cbf18c58..3a72d4fd0214e41fa60924b45697265b8143b1bd 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -193,6 +193,14 @@ void gen11_gt_irq_reset(struct intel_gt *gt)
        /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */
        intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK,   ~0);
        intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK,    ~0);
+       if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+               intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~0);
+       if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+               intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~0);
+       if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+               intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~0);
+       if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+               intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~0);
        intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK,   ~0);
        intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK,   ~0);
        if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
@@ -248,6 +256,14 @@ void gen11_gt_irq_postinstall(struct intel_gt *gt)
        /* Unmask irqs on RCS, BCS, VCS and VECS engines. */
        intel_uncore_write(uncore, GEN11_RCS0_RSVD_INTR_MASK, ~smask);
        intel_uncore_write(uncore, GEN11_BCS_RSVD_INTR_MASK, ~smask);
+       if (HAS_ENGINE(gt, BCS1) || HAS_ENGINE(gt, BCS2))
+               intel_uncore_write(uncore, XEHPC_BCS1_BCS2_INTR_MASK, ~dmask);
+       if (HAS_ENGINE(gt, BCS3) || HAS_ENGINE(gt, BCS4))
+               intel_uncore_write(uncore, XEHPC_BCS3_BCS4_INTR_MASK, ~dmask);
+       if (HAS_ENGINE(gt, BCS5) || HAS_ENGINE(gt, BCS6))
+               intel_uncore_write(uncore, XEHPC_BCS5_BCS6_INTR_MASK, ~dmask);
+       if (HAS_ENGINE(gt, BCS7) || HAS_ENGINE(gt, BCS8))
+               intel_uncore_write(uncore, XEHPC_BCS7_BCS8_INTR_MASK, ~dmask);
        intel_uncore_write(uncore, GEN11_VCS0_VCS1_INTR_MASK, ~dmask);
        intel_uncore_write(uncore, GEN11_VCS2_VCS3_INTR_MASK, ~dmask);
        if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index aa2c0974b02ce9adc2ddc6738283bf96b06d1ab0..fe09288a31457c5b23b9667563c53ca4a766eb95 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1529,6 +1529,10 @@
 #define GEN11_GUNIT_CSME_INTR_MASK             _MMIO(0x1900f4)
 #define GEN12_CCS0_CCS1_INTR_MASK              _MMIO(0x190100)
 #define GEN12_CCS2_CCS3_INTR_MASK              _MMIO(0x190104)
+#define XEHPC_BCS1_BCS2_INTR_MASK              _MMIO(0x190110)
+#define XEHPC_BCS3_BCS4_INTR_MASK              _MMIO(0x190114)
+#define XEHPC_BCS5_BCS6_INTR_MASK              _MMIO(0x190118)
+#define XEHPC_BCS7_BCS8_INTR_MASK              _MMIO(0x19011c)
 
 #define GEN12_SFC_DONE(n)                      _MMIO(0x1cc000 + (n) * 0x1000)