if (r)
                return r;
 
-       return 0;
+       adev->jpeg.supported_reset = AMDGPU_RESET_TYPE_PER_QUEUE;
+       r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
+
+       return r;
 }
 
 /**
        if (r)
                return r;
 
+       amdgpu_jpeg_sysfs_reset_mask_fini(adev);
+
        r = amdgpu_jpeg_sw_fini(adev);
 
        return r;
        return 0;
 }
 
+static int jpeg_v2_0_ring_reset(struct amdgpu_ring *ring, unsigned int vmid)
+{
+       jpeg_v2_0_stop(ring->adev);
+       jpeg_v2_0_start(ring->adev);
+       return amdgpu_ring_test_helper(ring);
+}
+
 static const struct amd_ip_funcs jpeg_v2_0_ip_funcs = {
        .name = "jpeg_v2_0",
        .early_init = jpeg_v2_0_early_init,
        .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
        .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
        .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
+       .reset = jpeg_v2_0_ring_reset,
 };
 
 static void jpeg_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev)