clk: sunxi-ng: h3: h5: Add minimal rate for video PLL

Although user manuals for H3 and H5 SoCs state that minimal rate
supported by video PLL is around 30 MHz, it seems that in reality
minimal rate is around 192 MHz.

Experiments showed that any rate below 96 MHz doesn't produce any video
output at all. Even at this frequency, stable output depends on right
factors. For example, when N = 4 and M = 1, output is stable and when N
= 8 and M = 2, it's not.

BSP clock driver suggest that minimum stable frequency is 192 MHz. That
would also be in line with A64 SoC, which has similar periphery.

Set minimal video PLL rate for H3/H5 to 192 MHz.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>

diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 29bc0566b776e7444f8a07c9a8660073a1ddadb8..b9f39078c0b28c5253b16f8074d31e300772a68b 100644 (file)
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -69,17 +69,18 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
                                       BIT(28), /* lock */
                                       CLK_SET_RATE_UNGATE);
 
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
-                                       "osc24M", 0x0010,
-                                       8, 7,           /* N */
-                                       0, 4,           /* M */
-                                       BIT(24),        /* frac enable */
-                                       BIT(25),        /* frac select */
-                                       270000000,      /* frac rate 0 */
-                                       297000000,      /* frac rate 1 */
-                                       BIT(31),        /* gate */
-                                       BIT(28),        /* lock */
-                                       CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
+                                           "osc24M", 0x0010,
+                                           192000000,  /* Minimum rate */
+                                           8, 7,       /* N */
+                                           0, 4,       /* M */
+                                           BIT(24),    /* frac enable */
+                                           BIT(25),    /* frac select */
+                                           270000000,  /* frac rate 0 */
+                                           297000000,  /* frac rate 1 */
+                                           BIT(31),    /* gate */
+                                           BIT(28),    /* lock */
+                                           CLK_SET_RATE_UNGATE);
 
 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
                                        "osc24M", 0x0018,