net: stmmac: mtl rx queue enabled as dcb or avb

This patch introduces the enabling of RX queues as DCB or as AVB based
on configuration.

Signed-off-by: Joao Pinto <jpinto@synopsys.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 4eeaa5c905f2393171ffd0b097aa6cc2660436ee..f61611c8e8b0602a17712c495262e3b2c60df94e 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -457,7 +457,7 @@ struct stmmac_ops {
        /* Enable and verify that the IPC module is supported */
        int (*rx_ipc)(struct mac_device_info *hw);
        /* Enable RX Queues */
-       void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);
+       void (*rx_queue_enable)(struct mac_device_info *hw, u8 mode, u32 queue);
        /* Program RX Algorithms */
        void (*prog_mtl_rx_algorithms)(struct mac_device_info *hw, u32 rx_alg);
        /* Program TX Algorithms */

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index fda6cfa7aba4709f9f9154ba1f9bd3a2def49472..21a696eda9ce0687fd35e5c91110b0faff0ae0d4 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -59,13 +59,17 @@ static void dwmac4_core_init(struct mac_device_info *hw, int mtu)
        writel(value, ioaddr + GMAC_INT_EN);
 }
 
-static void dwmac4_rx_queue_enable(struct mac_device_info *hw, u32 queue)
+static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
+                                  u8 mode, u32 queue)
 {
        void __iomem *ioaddr = hw->pcsr;
        u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
 
        value &= GMAC_RX_QUEUE_CLEAR(queue);
-       value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
+       if (mode == MTL_RX_AVB)
+               value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
+       else if (mode == MTL_RX_DCB)
+               value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
 
        writel(value, ioaddr + GMAC_RXQ_CTRL0);
 }

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 7b05cd3fce1c99c809c4502708e6c798029d052c..43036dabb9f9d528736c67e0e21be4ff92aac1b3 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1256,19 +1256,14 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
  */
 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv)
 {
-       int rx_count = priv->dma_cap.number_rx_queues;
-       int queue = 0;
-
-       /* If GMAC does not have multiple queues, then this is not necessary*/
-       if (rx_count == 1)
-               return;
+       u32 rx_queues_count = priv->plat->rx_queues_to_use;
+       int queue;
+       u8 mode;
 
-       /**
-        *  If the core is synthesized with multiple rx queues / multiple
-        *  dma channels, then rx queues will be disabled by default.
-        *  For now only rx queue 0 is enabled.
-        */
-       priv->hw->mac->rx_queue_enable(priv->hw, queue);
+       for (queue = 0; queue < rx_queues_count; queue++) {
+               mode = priv->plat->rx_queues_cfg[queue].mode_to_use;
+               priv->hw->mac->rx_queue_enable(priv->hw, mode, queue);
+       }
 }
 
 /**