#include <linux/module.h>
 #include <linux/of_device.h>
 #include <linux/of_dma.h>
+#include <linux/pm_runtime.h>
 #include <linux/reset.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
        stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
        clear_bit(mux->chan_id, dmamux->dma_inuse);
 
-       if (!IS_ERR(dmamux->clk))
-               clk_disable(dmamux->clk);
+       pm_runtime_put_sync(dev);
 
        spin_unlock_irqrestore(&dmamux->lock, flags);
 
 
        /* Set dma request */
        spin_lock_irqsave(&dmamux->lock, flags);
-       if (!IS_ERR(dmamux->clk)) {
-               ret = clk_enable(dmamux->clk);
-               if (ret < 0) {
-                       spin_unlock_irqrestore(&dmamux->lock, flags);
-                       dev_err(&pdev->dev, "clk_prep_enable issue: %d\n", ret);
-                       goto error;
-               }
+       ret = pm_runtime_get_sync(&pdev->dev);
+       if (ret < 0) {
+               spin_unlock_irqrestore(&dmamux->lock, flags);
+               goto error;
        }
        spin_unlock_irqrestore(&dmamux->lock, flags);
 
                dev_warn(&pdev->dev, "DMAMUX defaulting on %u requests\n",
                         stm32_dmamux->dmamux_requests);
        }
+       pm_runtime_get_noresume(&pdev->dev);
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
        iomem = devm_ioremap_resource(&pdev->dev, res);
        stm32_dmamux->dmarouter.route_free = stm32_dmamux_free;
 
        platform_set_drvdata(pdev, stm32_dmamux);
+       pm_runtime_set_active(&pdev->dev);
+       pm_runtime_enable(&pdev->dev);
 
        if (!IS_ERR(stm32_dmamux->clk)) {
                ret = clk_prepare_enable(stm32_dmamux->clk);
                }
        }
 
+       pm_runtime_get_noresume(&pdev->dev);
+
        /* Reset the dmamux */
        for (i = 0; i < stm32_dmamux->dma_requests; i++)
                stm32_dmamux_write(stm32_dmamux->iomem, STM32_DMAMUX_CCR(i), 0);
 
-       if (!IS_ERR(stm32_dmamux->clk))
-               clk_disable(stm32_dmamux->clk);
+       pm_runtime_put(&pdev->dev);
 
        return of_dma_router_register(node, stm32_dmamux_route_allocate,
                                     &stm32_dmamux->dmarouter);
 }
 
+#ifdef CONFIG_PM
+static int stm32_dmamux_runtime_suspend(struct device *dev)
+{
+       struct platform_device *pdev =
+               container_of(dev, struct platform_device, dev);
+       struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
+
+       clk_disable_unprepare(stm32_dmamux->clk);
+
+       return 0;
+}
+
+static int stm32_dmamux_runtime_resume(struct device *dev)
+{
+       struct platform_device *pdev =
+               container_of(dev, struct platform_device, dev);
+       struct stm32_dmamux_data *stm32_dmamux = platform_get_drvdata(pdev);
+       int ret;
+
+       ret = clk_prepare_enable(stm32_dmamux->clk);
+       if (ret) {
+               dev_err(&pdev->dev, "failed to prepare_enable clock\n");
+               return ret;
+       }
+
+       return 0;
+}
+#endif
+
+static const struct dev_pm_ops stm32_dmamux_pm_ops = {
+       SET_RUNTIME_PM_OPS(stm32_dmamux_runtime_suspend,
+                          stm32_dmamux_runtime_resume, NULL)
+};
+
 static const struct of_device_id stm32_dmamux_match[] = {
        { .compatible = "st,stm32h7-dmamux" },
        {},
        .driver = {
                .name = "stm32-dmamux",
                .of_match_table = stm32_dmamux_match,
+               .pm = &stm32_dmamux_pm_ops,
        },
 };