net: mvpp2: fix pkt coalescing int-threshold configuration

The packet coalescing interrupt threshold has separated registers
for different aggregated/cpu (sw-thread). The required value should
be loaded for every thread but not only for 1 current cpu.

Fixes: 213f428f5056 ("net: mvpp2: add support for TX interrupts and RX queue distribution modes")
Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Link: https://lore.kernel.org/r/1608748521-11033-1-git-send-email-stefanc@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index f20b31327027006d9450bb1ad6fec84b5eae39ad..4b1808acef5812a934aeed1b44a804bd4fdb9bb2 100644 (file)
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
@@ -2370,17 +2370,18 @@ static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port,
 static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,
                                   struct mvpp2_tx_queue *txq)
 {
-       unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());
+       unsigned int thread;
        u32 val;
 
        if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)
                txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;
 
        val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);
-       mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
-       mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
-
-       put_cpu();
+       /* PKT-coalescing registers are per-queue + per-thread */
+       for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {
+               mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);
+               mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);
+       }
 }
 
 static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)