void arc_reg_data_type_add(struct target *target,
struct arc_reg_data_type *data_type)
{
- LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
+ LOG_TARGET_DEBUG(target, "Adding %s reg_data_type", data_type->data_type.id);
struct arc_common *arc = target_to_arc(target);
assert(arc);
{
struct arc_common *arc = target_to_arc(target);
- LOG_DEBUG("Resetting internal variables of caches states");
+ LOG_TARGET_DEBUG(target, "Resetting internal variables of caches states");
/* Reset caches states. */
arc->dcache_flushed = false;
/* The only allowed ir_length is 4 for ARC jtag. */
if (tap->ir_length != 4) {
- LOG_ERROR("ARC jtag instruction length should be equal to 4");
+ LOG_TARGET_ERROR(target, "ARC jtag instruction length should be equal to 4");
return ERROR_FAIL;
}
sizeof(*std_types));
if (!std_types) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
return ERROR_FAIL;
}
}
arc->num_regs += 1;
- LOG_DEBUG(
+ LOG_TARGET_DEBUG(target,
"added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "",
uint32_t value;
if (reg->valid) {
- LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
reg->number, desc->name, target_buffer_get_u32(target, reg->value));
return ERROR_OK;
}
if (desc->is_core) {
/* Accessing to R61/R62 registers causes Jtag hang */
if (desc->arch_num == ARC_R61 || desc->arch_num == ARC_R62) {
- LOG_ERROR("It is forbidden to read core registers 61 and 62.");
+ LOG_TARGET_ERROR(target, "It is forbidden to read core registers 61 and 62");
return ERROR_FAIL;
}
CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
reg->dirty = false;
- LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
reg->number, desc->name, value);
/* Accessing to R61/R62 registers causes Jtag hang */
if (desc->is_core && (desc->arch_num == ARC_R61 ||
desc->arch_num == ARC_R62)) {
- LOG_ERROR("It is forbidden to write core registers 61 and 62.");
+ LOG_TARGET_ERROR(target, "It is forbidden to write core registers 61 and 62");
return ERROR_FAIL;
}
target_buffer_set_u32(target, reg->value, value);
- LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+ LOG_TARGET_DEBUG(target, "Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
reg->number, desc->name, value);
reg->valid = true;
struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
if (!cache || !reg_list) {
- LOG_ERROR("Not enough memory");
+ LOG_TARGET_ERROR(target, "Not enough memory");
goto fail;
}
(*cache_p) = cache;
if (list_empty(&arc->core_reg_descriptions)) {
- LOG_ERROR("No core registers were defined");
+ LOG_TARGET_ERROR(target, "No core registers were defined");
goto fail;
}
list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
- LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
reg_list[i].name, reg_list[i].group,
reg_list[i].feature->name);
}
if (list_empty(&arc->aux_reg_descriptions)) {
- LOG_ERROR("No aux registers were defined");
+ LOG_TARGET_ERROR(target, "No aux registers were defined");
goto fail;
}
list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
- LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
reg_list[i].name, reg_list[i].group,
reg_list[i].feature->name);
/* PC and DEBUG are essential so we search for them. */
if (!strcmp("pc", reg_desc->name)) {
if (arc->pc_index_in_cache != ULONG_MAX) {
- LOG_ERROR("Double definition of PC in configuration");
+ LOG_TARGET_ERROR(target, "Double definition of PC in configuration");
goto fail;
}
arc->pc_index_in_cache = i;
} else if (!strcmp("debug", reg_desc->name)) {
if (arc->debug_index_in_cache != ULONG_MAX) {
- LOG_ERROR("Double definition of DEBUG in configuration");
+ LOG_TARGET_ERROR(target, "Double definition of DEBUG in configuration");
goto fail;
}
arc->debug_index_in_cache = i;
if (arc->pc_index_in_cache == ULONG_MAX
|| arc->debug_index_in_cache == ULONG_MAX) {
- LOG_ERROR("`pc' and `debug' registers must be present in target description.");
+ LOG_TARGET_ERROR(target, "`pc' and `debug' registers must be present in target description");
goto fail;
}
unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
if (!cache || !reg_list) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
goto fail;
}
(*cache_p) = cache;
if (list_empty(&arc->bcr_reg_descriptions)) {
- LOG_ERROR("No BCR registers are defined");
+ LOG_TARGET_ERROR(target, "No BCR registers are defined");
goto fail;
}
* not real register. */
reg_list[i].exist = true;
- LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ LOG_TARGET_DEBUG(target, "reg n=%3li name=%3s group=%s feature=%s", i,
reg_list[i].name, reg_list[i].group,
reg_list[i].feature->name);
i += 1;
*reg_list = calloc(*reg_list_size, sizeof(struct reg *));
if (!*reg_list) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
return ERROR_FAIL;
}
reg_cache = reg_cache->next;
}
assert(i == arc->num_regs);
- LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
+ LOG_TARGET_DEBUG(target, "REG_CLASS_ALL: number of regs=%i", *reg_list_size);
} else {
unsigned long i = 0;
unsigned long gdb_reg_number = 0;
reg_cache = reg_cache->next;
}
*reg_list_size = i;
- LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
+ LOG_TARGET_DEBUG(target, "REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
}
return ERROR_OK;
{
struct reg_data_type_struct_field *field;
- LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
+ LOG_TARGET_DEBUG(target, "getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
/* Get register */
struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
if (!reg) {
- LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
+ LOG_TARGET_ERROR(target, "Requested register `%s' doesn't exist", reg_name);
return ERROR_ARC_REGISTER_NOT_FOUND;
}
static int arc_get_register_value(struct target *target, const char *reg_name,
uint32_t *value_ptr)
{
- LOG_DEBUG("reg_name=%s", reg_name);
+ LOG_TARGET_DEBUG(target, "reg_name=%s", reg_name);
struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
static int arc_set_register_value(struct target *target, const char *reg_name,
uint32_t value)
{
- LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
+ LOG_TARGET_DEBUG(target, "reg_name=%s value=0x%08" PRIx32, reg_name, value);
if (!(target && reg_name)) {
- LOG_ERROR("Arguments cannot be NULL.");
+ LOG_TARGET_ERROR(target, "Arguments cannot be NULL");
return ERROR_FAIL;
}
if (dccm_build_size0 == 0xF)
dccm_size <<= dccm_build_size1;
arc->dccm_end = arc->dccm_start + dccm_size;
- LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc->dccm_start, arc->dccm_end);
}
/* iccm0 start is located in highest 4 bits of aux_iccm */
arc->iccm0_start = aux_iccm & 0xF0000000;
arc->iccm0_end = arc->iccm0_start + iccm0_size;
- LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc->iccm0_start, arc->iccm0_end);
}
iccm1_size <<= iccm_build_size11;
arc->iccm1_start = aux_iccm & 0x0F000000;
arc->iccm1_end = arc->iccm1_start + iccm1_size;
- LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
arc->iccm1_start, arc->iccm1_end);
}
return ERROR_OK;
/* Configure some core features, depending on BCRs. */
static int arc_configure(struct target *target)
{
- LOG_DEBUG("Configuring ARC ICCM and DCCM");
+ LOG_TARGET_DEBUG(target, "Configuring ARC ICCM and DCCM");
/* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
if (debug_level >= LOG_LVL_DEBUG) {
- LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
+ LOG_TARGET_DEBUG(target, "core stopped (halted) debug-reg: 0x%08" PRIx32, value);
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
- LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+ LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
}
return ERROR_OK;
uint32_t value, irq_state;
struct arc_common *arc = target_to_arc(target);
- LOG_DEBUG("target->state: %s", target_state_name(target));
+ LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
if (target->state == TARGET_HALTED) {
- LOG_DEBUG("target was already halted");
+ LOG_TARGET_DEBUG(target, "target was already halted");
return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
- LOG_WARNING("target was in unknown state when halt was requested");
+ LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
if (target->state == TARGET_RESET) {
if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
- LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+ LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
} else {
target->debug_reason = DBG_REASON_DBGRQ;
/* some more debug information */
if (debug_level >= LOG_LVL_DEBUG) {
- LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
+ LOG_TARGET_DEBUG(target, "core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
- LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+ LOG_TARGET_DEBUG(target, "core STATUS32: 0x%08" PRIx32, value);
}
return ERROR_OK;
struct arc_common *arc = target_to_arc(target);
struct reg *reg_list = arc->core_and_aux_cache->reg_list;
- LOG_DEBUG("Saving aux and core registers values");
+ LOG_TARGET_DEBUG(target, "Saving aux and core registers values");
assert(reg_list);
/* It is assumed that there is at least one AUX register in the list, for
unsigned int aux_cnt = 0;
if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
retval = ERROR_FAIL;
goto exit;
}
if (core_cnt > 0) {
retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
if (retval != ERROR_OK) {
- LOG_ERROR("Attempt to read core registers failed.");
+ LOG_TARGET_ERROR(target, "Attempt to read core registers failed");
retval = ERROR_FAIL;
goto exit;
}
if (aux_cnt > 0) {
retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
if (retval != ERROR_OK) {
- LOG_ERROR("Attempt to read aux registers failed.");
+ LOG_TARGET_ERROR(target, "Attempt to read aux registers failed");
retval = ERROR_FAIL;
goto exit;
}
target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
reg->valid = true;
reg->dirty = false;
- LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
+ LOG_TARGET_DEBUG(target, "Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
i, arc_reg->name, core_values[core_cnt]);
core_cnt++;
}
target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
reg->valid = true;
reg->dirty = false;
- LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
+ LOG_TARGET_DEBUG(target, "Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
i, arc_reg->name, aux_values[aux_cnt]);
aux_cnt++;
}
if (actionpoint) {
if (!actionpoint->used)
- LOG_WARNING("Target halted by an unused actionpoint.");
+ LOG_TARGET_WARNING(target, "Target halted by an unused actionpoint");
if (actionpoint->type == ARC_AP_BREAKPOINT)
target->debug_reason = DBG_REASON_BREAKPOINT;
else if (actionpoint->type == ARC_AP_WATCHPOINT)
target->debug_reason = DBG_REASON_WATCHPOINT;
else
- LOG_WARNING("Unknown type of actionpoint.");
+ LOG_TARGET_WARNING(target, "Unknown type of actionpoint");
}
}
/* check for processor halted */
if (status & ARC_JTAG_STAT_RU) {
if (target->state != TARGET_RUNNING) {
- LOG_WARNING("target is still running!");
+ LOG_TARGET_WARNING(target, "target is still running");
target->state = TARGET_RUNNING;
}
return ERROR_OK;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
if (value & AUX_STATUS32_REG_HALT_BIT) {
- LOG_DEBUG("ARC core in halt or reset state.");
+ LOG_TARGET_DEBUG(target, "ARC core in halt or reset state");
/* Save context if target was not in reset state */
if (target->state == TARGET_RUNNING)
CHECK_RETVAL(arc_debug_entry(target));
target->state = TARGET_HALTED;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
} else {
- LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
+ LOG_TARGET_DEBUG(target, "Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
"target is still running");
}
} else if (target->state == TARGET_DEBUG_RUNNING) {
target->state = TARGET_HALTED;
- LOG_DEBUG("ARC core is in debug running mode");
+ LOG_TARGET_DEBUG(target, "ARC core is in debug running mode");
CHECK_RETVAL(arc_debug_entry(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
bool srst_asserted = false;
- LOG_DEBUG("target->state: %s", target_state_name(target));
+ LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
/* allow scripts to override the reset event */
if (target->state == TARGET_HALTED && !target->reset_halt) {
/* Resume the target and continue from the current
* PC register value. */
- LOG_DEBUG("Starting CPU execution after reset");
+ LOG_TARGET_DEBUG(target, "Starting CPU execution after reset");
CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
}
target->state = TARGET_RESET;
static int arc_deassert_reset(struct target *target)
{
- LOG_DEBUG("target->state: %s", target_state_name(target));
+ LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
/* deassert reset lines */
jtag_add_reset(0, 0);
CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
- LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
+ LOG_TARGET_DEBUG(target, "target state: %s; PC at: 0x%08" PRIx32,
target_state_name(target),
pc_value);
struct arc_common *arc = target_to_arc(target);
struct reg *reg_list = arc->core_and_aux_cache->reg_list;
- LOG_DEBUG("Restoring registers values");
+ LOG_TARGET_DEBUG(target, "Restoring registers values");
assert(reg_list);
const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
unsigned int aux_cnt = 0;
if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
retval = ERROR_FAIL;
goto exit;
}
struct reg *reg = &(reg_list[i]);
struct arc_reg_desc *arc_reg = reg->arch_info;
if (reg->valid && reg->exist && reg->dirty) {
- LOG_DEBUG("Will write regnum=%u", i);
+ LOG_TARGET_DEBUG(target, "Will write regnum=%u", i);
core_addrs[core_cnt] = arc_reg->arch_num;
core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
core_cnt += 1;
struct reg *reg = &(reg_list[arc->num_core_regs + i]);
struct arc_reg_desc *arc_reg = reg->arch_info;
if (reg->valid && reg->exist && reg->dirty) {
- LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
+ LOG_TARGET_DEBUG(target, "Will write regnum=%lu", arc->num_core_regs + i);
aux_addrs[aux_cnt] = arc_reg->arch_num;
aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
aux_cnt += 1;
if (core_cnt > 0) {
retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
if (retval != ERROR_OK) {
- LOG_ERROR("Attempt to write to core registers failed.");
+ LOG_TARGET_ERROR(target, "Attempt to write to core registers failed");
retval = ERROR_FAIL;
goto exit;
}
if (aux_cnt > 0) {
retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
if (retval != ERROR_OK) {
- LOG_ERROR("Attempt to write to aux registers failed.");
+ LOG_TARGET_ERROR(target, "Attempt to write to aux registers failed");
retval = ERROR_FAIL;
goto exit;
}
/* enable interrupts */
value |= SET_CORE_ENABLE_INTERRUPTS;
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
- LOG_DEBUG("interrupts enabled");
+ LOG_TARGET_DEBUG(target, "interrupts enabled");
} else {
/* disable interrupts */
value &= ~SET_CORE_ENABLE_INTERRUPTS;
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
- LOG_DEBUG("interrupts disabled");
+ LOG_TARGET_DEBUG(target, "interrupts disabled");
}
return ERROR_OK;
uint32_t value;
struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
- LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
+ LOG_TARGET_DEBUG(target, "current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
" debug_execution:%i", current, address, handle_breakpoints, debug_execution);
/* We need to reset ARC cache variables so caches
target_buffer_set_u32(target, pc->value, address);
pc->dirty = true;
pc->valid = true;
- LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
+ LOG_TARGET_DEBUG(target, "Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
}
if (!current)
CHECK_RETVAL(arc_restore_context(target));
- LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
+ LOG_TARGET_DEBUG(target, "Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
resume_pc, pc->dirty, pc->valid);
/* check if GDB tells to set our PC where to continue from */
if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
value = target_buffer_get_u32(target, pc->value);
- LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
+ LOG_TARGET_DEBUG(target, "resume Core (when start-core) with PC @:0x%08" PRIx32, value);
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
}
/* Single step past breakpoint at current address */
struct breakpoint *breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
- LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
+ LOG_TARGET_DEBUG(target, "skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
breakpoint->address);
CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
CHECK_RETVAL(arc_single_step_core(target));
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
- LOG_DEBUG("Core started to run");
+ LOG_TARGET_DEBUG(target, "Core started to run");
/* registers are now invalid */
register_cache_invalidate(arc->core_and_aux_cache);
if (!debug_execution) {
target->state = TARGET_RUNNING;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
- LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
+ LOG_TARGET_DEBUG(target, "target resumed at 0x%08" PRIx32, resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
- LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
+ LOG_TARGET_DEBUG(target, "target debug resumed at 0x%08" PRIx32, resume_pc);
}
return ERROR_OK;
{
struct arc_common *arc = target_to_arc(target);
- LOG_DEBUG("deinitialization of target");
+ LOG_TARGET_DEBUG(target, "deinitialization of target");
if (arc->core_aux_cache_built)
arc_free_reg_cache(arc->core_and_aux_cache);
if (arc->bcr_cache_built)
struct arc_common *arc = calloc(1, sizeof(*arc));
if (!arc) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
return ERROR_FAIL;
}
- LOG_DEBUG("Entering");
+ LOG_TARGET_DEBUG(target, "Entering");
CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
return ERROR_OK;
{
uint8_t value_buf[4];
if (!target_was_examined(target)) {
- LOG_ERROR("Target not examined yet");
+ LOG_TARGET_ERROR(target, "Target not examined yet");
return ERROR_FAIL;
}
- LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+ LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
instr);
if (target->endianness == TARGET_LITTLE_ENDIAN)
uint8_t value_buf[4];
if (!target_was_examined(target)) {
- LOG_ERROR("Target not examined yet");
+ LOG_TARGET_ERROR(target, "Target not examined yet");
return ERROR_FAIL;
}
else
*value = be_to_h_u32(value_buf);
- LOG_DEBUG("Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
+ LOG_TARGET_DEBUG(target, "Address: 0x%08" PRIx32 ", value: 0x%08" PRIx32, address,
*value);
return ERROR_OK;
if (control_tt != AP_AC_TT_DISABLE) {
if (arc->actionpoints_num_avail < 1) {
- LOG_ERROR("No free actionpoints, maximum amount is %u",
+ LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
struct breakpoint *breakpoint)
{
if (breakpoint->is_set) {
- LOG_WARNING("breakpoint already set");
+ LOG_TARGET_WARNING(target, "breakpoint already set");
return ERROR_OK;
}
if (breakpoint->type == BKPT_SOFT) {
- LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+ LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);
if (breakpoint->length == 4) {
uint32_t verify = 0xffffffff;
CHECK_RETVAL(arc_read_instruction_u32(target, breakpoint->address, &verify));
if (verify != ARC_SDBBP_32) {
- LOG_ERROR("Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
+ LOG_TARGET_ERROR(target, "Unable to set 32bit breakpoint at address @0x%" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_FAIL;
}
CHECK_RETVAL(target_read_u16(target, breakpoint->address, &verify));
if (verify != ARC_SDBBP_16) {
- LOG_ERROR("Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
+ LOG_TARGET_ERROR(target, "Unable to set 16bit breakpoint at address @0x%" TARGET_PRIxADDR
" - check that memory is read/writable", breakpoint->address);
return ERROR_FAIL;
}
} else {
- LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+ LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
}
if (bp_num >= arc->actionpoints_num) {
- LOG_ERROR("No free actionpoints, maximum amount is %u",
+ LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
ap_list[bp_num].bp_value = breakpoint->address;
ap_list[bp_num].type = ARC_AP_BREAKPOINT;
- LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
}
} else {
- LOG_DEBUG("ERROR: setting unknown breakpoint type");
+ LOG_TARGET_ERROR(target, "setting unknown breakpoint type");
return ERROR_FAIL;
}
int retval = ERROR_OK;
if (!breakpoint->is_set) {
- LOG_WARNING("breakpoint not set");
+ LOG_TARGET_WARNING(target, "breakpoint not set");
return ERROR_OK;
}
if (breakpoint->type == BKPT_SOFT) {
/* restore original instruction (kept in target endianness) */
- LOG_DEBUG("bpid: %" PRIu32, breakpoint->unique_id);
+ LOG_TARGET_DEBUG(target, "bpid: %" PRIu32, breakpoint->unique_id);
if (breakpoint->length == 4) {
uint32_t current_instr;
if (retval != ERROR_OK)
return retval;
} else {
- LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+ LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
" has been overwritten outside of debugger."
"Expected: @0x%x, got: @0x%" PRIx32,
breakpoint->address, ARC_SDBBP_32, current_instr);
if (retval != ERROR_OK)
return retval;
} else {
- LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
+ LOG_TARGET_WARNING(target, "Software breakpoint @0x%" TARGET_PRIxADDR
" has been overwritten outside of debugger. "
"Expected: 0x%04x, got: 0x%04" PRIx16,
breakpoint->address, ARC_SDBBP_16, current_instr);
}
} else {
- LOG_ERROR("Invalid breakpoint length: target supports only 2 or 4");
+ LOG_TARGET_ERROR(target, "Invalid breakpoint length: target supports only 2 or 4");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
breakpoint->is_set = false;
- } else if (breakpoint->type == BKPT_HARD) {
+ } else if (breakpoint->type == BKPT_HARD) {
struct arc_common *arc = target_to_arc(target);
struct arc_actionpoint *ap_list = arc->actionpoints_list;
unsigned int bp_num = breakpoint->number;
if (bp_num >= arc->actionpoints_num) {
- LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
+ LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
bp_num, breakpoint->unique_id);
return ERROR_OK;
}
ap_list[bp_num].used = 0;
ap_list[bp_num].bp_value = 0;
- LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %u",
+ LOG_TARGET_DEBUG(target, "bpid: %" PRIu32 " - released actionpoint ID: %u",
breakpoint->unique_id, bp_num);
}
} else {
- LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
- return ERROR_FAIL;
+ LOG_TARGET_ERROR(target, "unsetting unknown breakpoint type");
+ return ERROR_FAIL;
}
return retval;
int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
{
- LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
+ LOG_TARGET_DEBUG(target, "actionpoints=%" PRIu32, ap_num);
struct arc_common *arc = target_to_arc(target);
/* Make sure that there are no enabled actionpoints in target. */
arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
if (!arc->actionpoints_list) {
- LOG_ERROR("Unable to allocate memory");
+ LOG_TARGET_ERROR(target, "Unable to allocate memory");
return ERROR_FAIL;
}
return ERROR_OK;
ap_num++;
if (ap_num >= arc->actionpoints_num) {
- LOG_ERROR("No actionpoint free, maximum amount is %u",
+ LOG_TARGET_ERROR(target, "No actionpoint free, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
ap_list[ap_num].bp_value = 0;
}
} else {
- LOG_ERROR("Register actionpoint not found");
+ LOG_TARGET_ERROR(target, "Register actionpoint not found");
}
return retval;
}
struct arc_actionpoint *ap_list = arc->actionpoints_list;
if (watchpoint->is_set) {
- LOG_WARNING("watchpoint already set");
+ LOG_TARGET_WARNING(target, "watchpoint already set");
return ERROR_OK;
}
}
if (wp_num >= arc->actionpoints_num) {
- LOG_ERROR("No free actionpoints, maximum amount is %u",
+ LOG_TARGET_ERROR(target, "No free actionpoints, maximum amount is %u",
arc->actionpoints_num);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (watchpoint->length != 4) {
- LOG_ERROR("Only watchpoints of length 4 are supported");
+ LOG_TARGET_ERROR(target, "Only watchpoints of length 4 are supported");
return ERROR_TARGET_UNALIGNED_ACCESS;
}
enable = AP_AC_TT_READWRITE;
break;
default:
- LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
+ LOG_TARGET_ERROR(target, "BUG: watchpoint->rw neither read, write nor access");
return ERROR_FAIL;
}
ap_list[wp_num].bp_value = watchpoint->address;
ap_list[wp_num].type = ARC_AP_WATCHPOINT;
- LOG_DEBUG("wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 ", wp_num %u wp_value 0x%" PRIx32,
watchpoint->unique_id, wp_num, ap_list[wp_num].bp_value);
}
struct arc_actionpoint *ap_list = arc->actionpoints_list;
if (!watchpoint->is_set) {
- LOG_WARNING("watchpoint not set");
+ LOG_TARGET_WARNING(target, "watchpoint not set");
return ERROR_OK;
}
unsigned int wp_num = watchpoint->number;
if (wp_num >= arc->actionpoints_num) {
- LOG_DEBUG("Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
+ LOG_TARGET_DEBUG(target, "Invalid actionpoint ID: %u in watchpoint: %" PRIu32,
wp_num, watchpoint->unique_id);
return ERROR_OK;
}
ap_list[wp_num].used = 0;
ap_list[wp_num].bp_value = 0;
- LOG_DEBUG("wpid: %" PRIu32 " - releasing actionpoint ID: %u",
+ LOG_TARGET_DEBUG(target, "wpid: %" PRIu32 " - releasing actionpoint ID: %u",
watchpoint->unique_id, wp_num);
}
if (actionpoint) {
if (!actionpoint->used)
- LOG_WARNING("Target halted by unused actionpoint.");
+ LOG_TARGET_WARNING(target, "Target halted by unused actionpoint");
/* If this check fails - that is some sort of an error in OpenOCD. */
if (actionpoint->type != ARC_AP_WATCHPOINT)
- LOG_WARNING("Target halted by breakpoint, but is treated as a watchpoint.");
+ LOG_TARGET_WARNING(target, "Target halted by breakpoint, but is treated as a watchpoint");
for (struct watchpoint *watchpoint = target->watchpoints;
watchpoint;
watchpoint = watchpoint->next) {
if (actionpoint->bp_value == watchpoint->address) {
*hit_watchpoint = watchpoint;
- LOG_DEBUG("Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
+ LOG_TARGET_DEBUG(target, "Hit watchpoint, wpid: %" PRIu32 ", watchpoint num: %u",
watchpoint->unique_id, watchpoint->number);
return ERROR_OK;
}
value &= ~SET_CORE_AE_BIT; /* clear the AE bit */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG,
value));
- LOG_DEBUG(" [status32:0x%08" PRIx32 "]", value);
+ LOG_TARGET_DEBUG(target, " [status32:0x%08" PRIx32 "]", value);
/* Doing read-modify-write, because DEBUG might contain manually set
* bits like UB or ED, which should be preserved. */
value |= SET_CORE_SINGLE_INSTR_STEP; /* set the IS bit */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
value));
- LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
+ LOG_TARGET_DEBUG(target, "core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);
} else { /* disable core debug step mode */
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
value &= ~SET_CORE_SINGLE_INSTR_STEP; /* clear the IS bit */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG,
value));
- LOG_DEBUG("core debug step mode disabled");
+ LOG_TARGET_DEBUG(target, "core debug step mode disabled");
}
return ERROR_OK;
pc->valid = true;
}
- LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "Target steps one instruction from PC=0x%" PRIx32,
buf_get_u32(pc->value, 0, 32));
/* the front-end may request us not to handle breakpoints */
if (breakpoint)
CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
- LOG_DEBUG("target stepped ");
+ LOG_TARGET_DEBUG(target, "target stepped");
target->state = TARGET_HALTED;
if (!arc->has_icache || arc->icache_invalidated)
return ERROR_OK;
- LOG_DEBUG("Invalidating I$.");
+ LOG_TARGET_DEBUG(target, "Invalidating I$");
value = IC_IVIC_INVALIDATE; /* invalidate I$ */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
if (!arc->has_dcache || arc->dcache_invalidated)
return ERROR_OK;
- LOG_DEBUG("Invalidating D$.");
+ LOG_TARGET_DEBUG(target, "Invalidating D$");
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
dc_ctrl_value = value;
if (!arc->has_l2cache || arc->l2cache_invalidated)
return ERROR_OK;
- LOG_DEBUG("Invalidating L2$.");
+ LOG_TARGET_DEBUG(target, "Invalidating L2$");
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
slc_ctrl_value = value;
/* Wait until invalidate operation ends */
do {
- LOG_DEBUG("Waiting for invalidation end.");
+ LOG_TARGET_DEBUG(target, "Waiting for invalidation end");
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
} while (value & L2_CTRL_BS);
if (!arc->has_dcache || arc->dcache_flushed)
return ERROR_OK;
- LOG_DEBUG("Flushing D$.");
+ LOG_TARGET_DEBUG(target, "Flushing D$");
/* Store current value of DC_CTRL */
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
if (!arc->has_l2cache || arc->l2cache_flushed)
return ERROR_OK;
- LOG_DEBUG("Flushing L2$.");
+ LOG_TARGET_DEBUG(target, "Flushing L2$");
/* Flush L2 cache */
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
/* Wait until flush operation ends */
do {
- LOG_DEBUG("Waiting for flushing end.");
+ LOG_TARGET_DEBUG(target, "Waiting for flushing end");
CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
} while (value & L2_CTRL_BS);
projects / users / borneoa / openocd-next.git / commitdiff