gva_t vaddr_accessed;
        pgd_t *pgdir;
 
-       u8 io_gpr; /* GPR used as IO source/target */
+       u16 io_gpr; /* GPR used as IO source/target */
        u8 mmio_host_swabbed;
        u8 mmio_sign_extend;
        /* conversion between single and double precision */
         */
        u8 mmio_vsx_copy_nums;
        u8 mmio_vsx_offset;
-       u8 mmio_vsx_tx_sx_enabled;
        u8 mmio_vmx_copy_nums;
        u8 mmio_vmx_offset;
        u8 mmio_copy_type;
 #define KVMPPC_VCPU_BUSY_IN_HOST       2
 
 /* Values for vcpu->arch.io_gpr */
-#define KVM_MMIO_REG_MASK      0x001f
-#define KVM_MMIO_REG_EXT_MASK  0xffe0
+#define KVM_MMIO_REG_MASK      0x003f
+#define KVM_MMIO_REG_EXT_MASK  0xffc0
 #define KVM_MMIO_REG_GPR       0x0000
-#define KVM_MMIO_REG_FPR       0x0020
-#define KVM_MMIO_REG_QPR       0x0040
-#define KVM_MMIO_REG_FQPR      0x0060
-#define KVM_MMIO_REG_VSX       0x0080
-#define KVM_MMIO_REG_VMX       0x00c0
+#define KVM_MMIO_REG_FPR       0x0040
+#define KVM_MMIO_REG_QPR       0x0080
+#define KVM_MMIO_REG_FQPR      0x00c0
+#define KVM_MMIO_REG_VSX       0x0100
+#define KVM_MMIO_REG_VMX       0x0180
 
 #define __KVM_HAVE_ARCH_WQP
 #define __KVM_HAVE_CREATE_DEVICE
 
         * if mmio_vsx_tx_sx_enabled == 1, copy data between
         * VSR[32..63] and memory
         */
-       vcpu->arch.mmio_vsx_tx_sx_enabled = get_tx_or_sx(inst);
        vcpu->arch.mmio_vsx_copy_nums = 0;
        vcpu->arch.mmio_vsx_offset = 0;
        vcpu->arch.mmio_copy_type = KVMPPC_VSX_COPY_NONE;
                        }
 
                        emulated = kvmppc_handle_vsx_load(run, vcpu,
-                                       KVM_MMIO_REG_VSX | (op.reg & 0x1f),
-                                       io_size_each, 1, op.type & SIGNEXT);
+                                       KVM_MMIO_REG_VSX|op.reg, io_size_each,
+                                       1, op.type & SIGNEXT);
                        break;
                }
 #endif
                        }
 
                        emulated = kvmppc_handle_vsx_store(run, vcpu,
-                                       op.reg & 0x1f, io_size_each, 1);
+                                       op.reg, io_size_each, 1);
                        break;
                }
 #endif
 
        if (offset == -1)
                return;
 
-       if (vcpu->arch.mmio_vsx_tx_sx_enabled) {
-               val.vval = VCPU_VSX_VR(vcpu, index);
+       if (index >= 32) {
+               val.vval = VCPU_VSX_VR(vcpu, index - 32);
                val.vsxval[offset] = gpr;
-               VCPU_VSX_VR(vcpu, index) = val.vval;
+               VCPU_VSX_VR(vcpu, index - 32) = val.vval;
        } else {
                VCPU_VSX_FPR(vcpu, index, offset) = gpr;
        }
        union kvmppc_one_reg val;
        int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
 
-       if (vcpu->arch.mmio_vsx_tx_sx_enabled) {
-               val.vval = VCPU_VSX_VR(vcpu, index);
+       if (index >= 32) {
+               val.vval = VCPU_VSX_VR(vcpu, index - 32);
                val.vsxval[0] = gpr;
                val.vsxval[1] = gpr;
-               VCPU_VSX_VR(vcpu, index) = val.vval;
+               VCPU_VSX_VR(vcpu, index - 32) = val.vval;
        } else {
                VCPU_VSX_FPR(vcpu, index, 0) = gpr;
                VCPU_VSX_FPR(vcpu, index, 1) = gpr;
        union kvmppc_one_reg val;
        int index = vcpu->arch.io_gpr & KVM_MMIO_REG_MASK;
 
-       if (vcpu->arch.mmio_vsx_tx_sx_enabled) {
+       if (index >= 32) {
                val.vsx32val[0] = gpr;
                val.vsx32val[1] = gpr;
                val.vsx32val[2] = gpr;
                val.vsx32val[3] = gpr;
-               VCPU_VSX_VR(vcpu, index) = val.vval;
+               VCPU_VSX_VR(vcpu, index - 32) = val.vval;
        } else {
                val.vsx32val[0] = gpr;
                val.vsx32val[1] = gpr;
        if (offset == -1)
                return;
 
-       if (vcpu->arch.mmio_vsx_tx_sx_enabled) {
-               val.vval = VCPU_VSX_VR(vcpu, index);
+       if (index >= 32) {
+               val.vval = VCPU_VSX_VR(vcpu, index - 32);
                val.vsx32val[offset] = gpr32;
-               VCPU_VSX_VR(vcpu, index) = val.vval;
+               VCPU_VSX_VR(vcpu, index - 32) = val.vval;
        } else {
                dword_offset = offset / 2;
                word_offset = offset % 2;
                        break;
                }
 
-               if (!vcpu->arch.mmio_vsx_tx_sx_enabled) {
+               if (rs < 32) {
                        *val = VCPU_VSX_FPR(vcpu, rs, vsx_offset);
                } else {
-                       reg.vval = VCPU_VSX_VR(vcpu, rs);
+                       reg.vval = VCPU_VSX_VR(vcpu, rs - 32);
                        *val = reg.vsxval[vsx_offset];
                }
                break;
                        break;
                }
 
-               if (!vcpu->arch.mmio_vsx_tx_sx_enabled) {
+               if (rs < 32) {
                        dword_offset = vsx_offset / 2;
                        word_offset = vsx_offset % 2;
                        reg.vsxval[0] = VCPU_VSX_FPR(vcpu, rs, dword_offset);
                        *val = reg.vsx32val[word_offset];
                } else {
-                       reg.vval = VCPU_VSX_VR(vcpu, rs);
+                       reg.vval = VCPU_VSX_VR(vcpu, rs - 32);
                        *val = reg.vsx32val[vsx_offset];
                }
                break;