* Add support for Windriver ppmc8260 board

  Note: this flash driver uses Common Flash Interface to determine
  the geometry of the flash chips!
  Patch by Brad Kemp, 18 Feb 2002

* Support "real" hardware for SXNI855T configuration.
  Patch by Dave Ellis, 12 Feb 2002

* Fix flash on the FLAGADM
  Patch by Kári Davíðsson, 8 Feb 2002

diff --git a/CHANGELOG b/CHANGELOG
index 0ac237bf7ab567e660759e55639d928e414d0b81..fa1038442e06bc95fcc0d8d31e184ce85fc563ba 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,17 @@
 Modifications for 1.1.5:
 ======================================================================
 
+* Add support for Windriver ppmc8260 board
+  Note: this flash driver uses Common Flash Interface to determine
+  the geometry of the flash chips!
+  Patch by Brad Kemp, 18 Feb 2002
+
+* Support "real" hardware for SXNI855T configuration.
+  Patch by Dave Ellis, 12 Feb 2002
+  
+* Fix flash on the FLAGADM
+  Patch by Kári Davíðsson, 8 Feb 2002
+
 * Improved (unified) support for multiple ethernet interfaces
   Now tested on PCIPPCx and Sandpoint 8240
   

diff --git a/CREDITS b/CREDITS
index 43edb3328375c9d2d531d319786300544d214d05..0d8b8c706ec73a35167539c604bd9155242373d1 100644 (file)
--- a/CREDITS
+++ b/CREDITS
@@ -132,6 +132,10 @@ N: Yoo. Jonghoon
 E: yooth@ipone.co.kr
 D: Added port to the RPXlite board
 
+N: Brad Kemp
+E: Brad.Kemp@seranoa.com
+D: Port to Windriver ppmc8260 board
+
 N: Thomas Koeller
 E: tkoeller@gmx.net
 D: Port to Motorola Sandpoint 3 (MPC8240)

diff --git a/MAKEALL b/MAKEALL
index b1b17166aaa90da60946ed1651f4483663214e9c..b196b47c9ca0ed4b7658babb0d022b8f9028976a 100755 (executable)
--- a/MAKEALL
+++ b/MAKEALL
@@ -54,8 +54,8 @@ LIST_824x="   \
 
 LIST_8260="    \
        cogent_mpc8260  ep8260          gw8260          hymod           \
-       IPHASE4539      MPC8260ADS      PM826           RPXsuper        \
-       rsdproto        sbc8260         TQM8260                         \
+       IPHASE4539      MPC8260ADS      PM826           ppmc8260        \
+       RPXsuper        rsdproto        sbc8260         TQM8260         \
 "
 
 #########################################################################

diff --git a/Makefile b/Makefile
index 47462a164aa9f9e43ee9b436271e036227164931..7bc9f1ccb802dda3530df8f0453099625d281c6c 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -670,6 +670,14 @@ PM826_config: unconfig
        echo "CPU   = mpc8260"  >>config.mk ;   \
        echo "#include <config_$(@:_config=).h>" >config.h
 
+ppmc8260_config:       unconfig
+       @echo "Configuring for $(@:_config=) Board..." ; \
+       cd ./include ;                          \
+       echo "ARCH  = ppc"      > config.mk ;   \
+       echo "BOARD = ppmc8260" >>config.mk ;   \
+       echo "CPU   = mpc8260"  >>config.mk ;   \
+       echo "#include <config_$(@:_config=).h>" >config.h
+
 RPXsuper_config:       unconfig
        @echo "Configuring for $(@:_config=) Board..." ; \
        cd ./include ;                          \

diff --git a/README b/README
index aa17727a3ef019721334d14e1d6d33fd4786a569..46794a09b1f5768cefac19265d3d328a59ca0b1e 100644 (file)
--- a/README
+++ b/README
@@ -1365,7 +1365,8 @@ defines the following image properties:
 
 * Target Operating System (Provisions for OpenBSD, NetBSD, FreeBSD,
   4.4BSD, Linux, SVR4, Esix, Solaris, Irix, SCO, Dell, NCR, VxWorks,
-  LynxOS, pSOS, QNX; Currently supported: Linux).
+  LynxOS, pSOS, QNX;
+  Currently supported: Linux, NetBSD, VxWorks, QNX).
 * Target CPU Architecture (Provisions for Alpha, ARM, Intel x86,
   IA64, MIPS, MIPS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit;
   Currently supported: PowerPC).

diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
index 636e04e11732478df2d5d7957b5d1a518bbd3927..0de66fc7c7fb6ad428803b057812655cc1b08e65 100644 (file)
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -48,7 +48,7 @@ flash_info_t  flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
 /*-----------------------------------------------------------------------
  * Functions
  */
-static ulong flash_get_size (int, vu_long *addr, flash_info_t *info);
+static ulong flash_get_size (int portwidth, vu_long *addr, flash_info_t *info);
 static int write_word (flash_info_t *info, ulong dest, ulong data);
 static void flash_get_offsets (ulong base, flash_info_t *info);
 
@@ -255,7 +255,7 @@ static inline void flash_cmd(int width, volatile unsigned char *addr, int offset
 }
 
 static ulong
-flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
+flash_get_size (int portwidth, vu_long *addr, flash_info_t *info)
 {
        short i;
        volatile unsigned char *caddr = (unsigned char *)addr;
@@ -264,12 +264,12 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
        char old[2], save;
        ulong id, manu, base = (ulong)addr;
 
-       info->width=fl_width;
+       info->portwidth=portwidth;
 
        save = *caddr;
 
-       flash_cmd(fl_width,caddr,0,0xf0);
-       flash_cmd(fl_width,caddr,0,0xf0);
+       flash_cmd(portwidth,caddr,0,0xf0);
+       flash_cmd(portwidth,caddr,0,0xf0);
 
        udelay(10);
 
@@ -278,8 +278,8 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
 
 
        if(old[0]!=0xf0) {
-           flash_cmd(fl_width,caddr,0,0xf0);
-           flash_cmd(fl_width,caddr,0,0xf0);
+           flash_cmd(portwidth,caddr,0,0xf0);
+           flash_cmd(portwidth,caddr,0,0xf0);
 
            udelay(10);
 
@@ -306,15 +306,15 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
                flash_get_offsets(base, info);
                return info->size;
            }
-           flash_cmd(fl_width,caddr,0,0xf0);
+           flash_cmd(portwidth,caddr,0,0xf0);
 
            udelay(10);
        }
 
        /* Write auto select command: read Manufacturer ID */
-       flash_cmd(fl_width,caddr,0x555,0xAA);
-       flash_cmd(fl_width,caddr,0x2AA,0x55);
-       flash_cmd(fl_width,caddr,0x555,0x90);
+       flash_cmd(portwidth,caddr,0x555,0xAA);
+       flash_cmd(portwidth,caddr,0x2AA,0x55);
+       flash_cmd(portwidth,caddr,0x555,0x90);
 
        udelay(10);
 
@@ -330,12 +330,12 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
 #ifdef DEBUG
        } else {
            printf("%px%d: %02x:%02x -> %02x:%02x\n",
-                   caddr, fl_width, old[0], old[1],
+                   caddr, portwidth, old[0], old[1],
                    caddr[0], caddr[1]);
 #endif
        }
 
-       switch(fl_width) {
+       switch(portwidth) {
            case 1:
                manu = caddr[0];
                manu |= manu<<16;
@@ -382,36 +382,42 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
                    info->flash_id += FLASH_AM400T;
                    info->sector_count = 11;
                    info->size = 0x00100000;
+                   info->chipwidth=1;
                    break;                              /* => 1 MB      */
 
            case AMD_ID_LV400B:
                    info->flash_id += FLASH_AM400B;
                    info->sector_count = 11;
                    info->size = 0x00100000;
+                   info->chipwidth=1;
                    break;                              /* => 1 MB      */
 
            case AMD_ID_LV800T:
                    info->flash_id += FLASH_AM800T;
                    info->sector_count = 19;
                    info->size = 0x00200000;
+                   info->chipwidth=1;
                    break;                              /* => 2 MB      */
 
            case AMD_ID_LV800B:
                    info->flash_id += FLASH_AM800B;
                    info->sector_count = 19;
                    info->size = 0x00200000;
+                   info->chipwidth=1;
                    break;                              /* => 2 MB      */
 
            case AMD_ID_LV160T:
                    info->flash_id += FLASH_AM160T;
                    info->sector_count = 35;
                    info->size = 0x00400000;
+                   info->chipwidth=1;
                    break;                              /* => 4 MB      */
 
            case AMD_ID_LV160B:
                    info->flash_id += FLASH_AM160B;
                    info->sector_count = 35;
                    info->size = 0x00400000;
+                   info->chipwidth=1;
                    break;                              /* => 4 MB      */
 #if 0  /* enable when device IDs are available */
            case AMD_ID_LV320T:
@@ -430,25 +436,29 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
                    info->flash_id += FLASH_AM040;
                    info->sector_count = 8;
                    info->size = 0x80000;
+                   info->chipwidth=1;
                    break;
                    
            case INTEL_ID_28F640J3A:
                    info->flash_id += FLASH_28F640J3A;
                    info->sector_count = 64;
                    info->size = 128*1024 * 64; /* 128kbytes x 64 blocks */
-                   if(fl_width==4) info->size*=2;      /* 2x16 */
+                   info->chipwidth=2;
+                   if(portwidth==4) info->size*=2;     /* 2x16 */
                    break;
 
            case INTEL_ID_28F128J3A:
                    info->flash_id += FLASH_28F128J3A;
                    info->sector_count = 128;
                    info->size = 128*1024 * 128; /* 128kbytes x 128 blocks */
-                   if(fl_width==4) info->size*=2;      /* 2x16 */
+                   info->chipwidth=2;
+                   if(portwidth==4) info->size*=2;     /* 2x16 */
                    break;
 
            default:
                    printf("Unknown id %lx:[%lx]\n", manu, id);
                    info->flash_id = FLASH_UNKNOWN;
+                   info->chipwidth=1;
                    return (0);                 /* => no or unknown flash */
 
        }
@@ -490,9 +500,9 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
                caddr = (volatile unsigned char *)(info->start[i]);
                saddr = (volatile unsigned short *)(info->start[i]);
                laddr = (volatile unsigned long *)(info->start[i]);
-               if(fl_width==1) 
+               if(portwidth==1) 
                    info->protect[i] = caddr[2] & 1;
-               else if(fl_width==2) 
+               else if(portwidth==2) 
                    info->protect[i] = saddr[2] & 1;
                else
                    info->protect[i] = laddr[2] & 1;
@@ -504,7 +514,7 @@ flash_get_size (int fl_width, vu_long *addr, flash_info_t *info)
        if (info->flash_id != FLASH_UNKNOWN) {
                caddr = (volatile unsigned char *)info->start[0];
 
-               flash_cmd(fl_width,caddr,0,0xF0);       /* reset bank */
+               flash_cmd(portwidth,caddr,0,0xF0);      /* reset bank */
        }
 
        return (info->size);
@@ -519,7 +529,7 @@ flash_erase (flash_info_t *info, int s_first, int s_last)
        ulong start, now, last;
 
        /* TODO: 2x16 unsupported */
-       if(info->width==4) return 1;
+       if(info->portwidth==4) return 1;
 
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
@@ -574,17 +584,17 @@ flash_erase (flash_info_t *info, int s_first, int s_last)
        /* Disable interrupts which might cause a timeout here */
        flag = disable_interrupts();
 
-       flash_cmd(info->width,addr,0x555,0xAA);
-       flash_cmd(info->width,addr,0x2AA,0x55);
-       flash_cmd(info->width,addr,0x555,0x80);
-       flash_cmd(info->width,addr,0x555,0xAA);
-       flash_cmd(info->width,addr,0x2AA,0x55);
+       flash_cmd(info->portwidth,addr,0x555,0xAA);
+       flash_cmd(info->portwidth,addr,0x2AA,0x55);
+       flash_cmd(info->portwidth,addr,0x555,0x80);
+       flash_cmd(info->portwidth,addr,0x555,0xAA);
+       flash_cmd(info->portwidth,addr,0x2AA,0x55);
 
        /* Start erase on unprotected sectors */
        for (sect = s_first; sect<=s_last; sect++) {
                if (info->protect[sect] == 0) { /* not protected */
                        addr = (char *)(info->start[sect]);
-                       flash_cmd(info->width,addr,0,0x30);
+                       flash_cmd(info->portwidth,addr,0,0x30);
                        l_sect = sect;
                }
        }
@@ -621,8 +631,8 @@ flash_erase (flash_info_t *info, int s_first, int s_last)
 DONE:
        /* reset to read mode */
        addr = (volatile unsigned char *)info->start[0];
-       flash_cmd(info->width,addr,0,0xf0);
-       flash_cmd(info->width,addr,0,0xf0);
+       flash_cmd(info->portwidth,addr,0,0xf0);
+       flash_cmd(info->portwidth,addr,0,0xf0);
 
        printf (" done\n");
        return 0;
@@ -642,7 +652,7 @@ write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
        ulong cp, wp, data;
        int i, l, rc;
 
-       if(info->width==4) return 1;
+       if(info->portwidth==4) return 1;
 
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 0;
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
@@ -723,7 +733,7 @@ write_word (flash_info_t *info, ulong dest, ulong data)
        ulong start;
        int flag, i;
 
-       if(info->width==4) return 1;
+       if(info->portwidth==4) return 1;
 
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
        if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {

diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
index 8f595538c9de2978d48fa31c66ad19f589db2974..2954c6661966b396a47ff833cac2dfb53666bb2a 100644 (file)
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -96,7 +96,7 @@ static u32 size_bar(int host, int barnum, int device, PCI_BAR *bar)
     u32 detect, size=0;
 
     pciWriteConfigReg(host,BAR_REG[barnum],device,0x0);
-    if((((detect=pciReadConfigReg(host,BAR_REG[barnum],device))&~1)!=0x0)) {
+    if((((detect=pciReadConfigReg(host,BAR_REG[barnum],device))&~9)!=0x0)) {
        static const int ide_bar[]={8,4,8,4,0,0};
         u32 classCode = pciReadConfigReg(host,PCI_CLASS_CODE_AND_REVISION_ID,
                                           device);

diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c
index 50281650cd1a9d2217badea0b3b495a825562237..a56d7b77003f00b94c2fdbbe7a720b97246abfdf 100644 (file)
--- a/board/flagadm/flash.c
+++ b/board/flagadm/flash.c
@@ -30,14 +30,12 @@ flash_info_t        flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
 /*-----------------------------------------------------------------------
  * Functions
  */
-static ulong flash_recognize (vu_long *base);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_geometry (vu_long *base, flash_info_t *info);
-static void flash_unprotect(flash_info_t *info);
-static int _flash_real_protect(flash_info_t *info, long sector, int prot);
+ulong flash_recognize (vu_long *base);
+int write_word (flash_info_t *info, ulong dest, ulong data);
+void flash_get_geometry (vu_long *base, flash_info_t *info);
+void flash_unprotect(flash_info_t *info);
+int _flash_real_protect(flash_info_t *info, long idx, int on);
 
-/*-----------------------------------------------------------------------
- */
 
 unsigned long flash_init (void)
 {
@@ -63,14 +61,18 @@ unsigned long flash_init (void)
 
        if (rec == FLASH_UNKNOWN) {
                printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-                       flash_info[0].size, flash_info[0].size >> 20);
+                               flash_info[0].size, flash_info[0].size<<20);
        }
 
+#if CFG_FLASH_PROTECTION
        /*Unprotect all the flash memory*/
        flash_unprotect(&flash_info[0]);
+#endif
 
        *((vu_short*)CFG_FLASH_BASE) = 0xffff;
 
+       return (flash_info[0].size);
+
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
        /* monitor protection ON by default */
        flash_protect(FLAG_PROTECT_SET,
@@ -90,18 +92,17 @@ unsigned long flash_init (void)
 }
 
 
-int flash_get_protect_status(flash_info_t * info, long sector)
+int flash_get_protect_status(flash_info_t * info, long idx)
 {
        vu_short * base;
        ushort res;
 
 #if DEBUG
-       printf ("\n Attempting to set protection info with %d sectors\n",
-               info->sector_count);
+       printf("\n Attempting to set protection info with %d sectors\n", info->sector_count);
 #endif
 
 
-       base = (vu_short*)info->start[sector];
+       base = (vu_short*)info->start[idx];
 
        *(base) = 0xffff;
 
@@ -112,11 +113,13 @@ int flash_get_protect_status(flash_info_t * info, long sector)
 
        if(res != 0)
                res = 1;
+       else
+               res = 0;
 
        return res;
 }
 
-static void flash_get_geometry (vu_long *base, flash_info_t *info)
+void flash_get_geometry (vu_long *base, flash_info_t *info)
 {
        int i,j;
        ulong ner = 0;
@@ -155,7 +158,8 @@ static void flash_get_geometry (vu_long *base, flash_info_t *info)
 
        info->sector_count = 0;
 
-       for(i = 0; i < ner; i++) {
+       for(i = 0; i < ner; i++)
+       {
                uint s;
                uint count;
                uint t1,t2,t3,t4;
@@ -169,16 +173,15 @@ static void flash_get_geometry (vu_long *base, flash_info_t *info)
                t3 = sb[0x2f + i*4];
                t4 = sb[0x30 + i*4];
 
-               /*sector count*/
-               count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1;
-               /*Sector size*/
-               s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;
+               count = ((t1 & 0x00ff) | (((t2 & 0x00ff) << 8) & 0xff00) )+ 1; /*sector count*/
+               s = ((t3 & 0x00ff) | (((t4 & 0x00ff) << 8) & 0xff00)) * 256;; /*Sector size*/
 
 #if DEBUG
                printf("count and size %x, %x\n", count, s);
                printf("sector count for erase region %d is %d\n", i, count);
 #endif
-               for(j = 0; j < count; j++) {
+               for(j = 0; j < count; j++)
+               {
 #if DEBUG
                        printf("%x, ", (uint)offset);
 #endif
@@ -188,11 +191,9 @@ static void flash_get_geometry (vu_long *base, flash_info_t *info)
                info->sector_count += count;
        }
 
-       if ((offset - (ulong)base) != info->size) {
-               printf ("WARNING "
-                       "reported size %x does not match to calculted size %x.\n",
-                       (uint)info->size, (uint)(offset - (ulong)base) );
-       }
+       if ((offset - (ulong)base) != info->size)
+               printf("WARNING reported size %x does not match to calculted size %x.\n"
+                               , (uint)info->size, (uint)(offset - (ulong)base) );
 
        /* Next check if there are any sectors protected.*/
 
@@ -223,12 +224,12 @@ void flash_print_info  (flash_info_t *info)
        }
 
        switch (info->flash_id & FLASH_TYPEMASK) {
-       case INTEL_ID_28F320C3 & FLASH_TYPEMASK:
+       case INTEL_ID_28F320C3B & FLASH_TYPEMASK:
                printf ("28F320RC3(4 MB)\n");
                break;
-       case INTEL_ID_28F320J3A & FLASH_TYPEMASK:
+       case INTEL_ID_28F320J3A:
                printf("28F320J3A (4 MB)\n");
-                       break;
+               break;
        default:
                printf ("Unknown Chip Type\n");
                        break;
@@ -240,17 +241,17 @@ void flash_print_info  (flash_info_t *info)
        printf ("  Sector Start Addresses:");
        for (i=0; i<info->sector_count; ++i) {
                if ((i % 4) == 0)
-                       puts ("\n   ");
+                       printf ("\n   ");
                printf ("  %02d %08lX%s",
                        i, info->start[i],
-                       info->protect[i] ? " (RO)" : "     "
+                       info->protect[i]!=0 ? " (RO)" : "     "
                );
        }
        printf ("\n");
        return ;
 }
 
-static ulong flash_recognize (vu_long *base)
+ulong flash_recognize (vu_long *base)
 {
        ulong id;
        ulong res = FLASH_UNKNOWN;
@@ -261,14 +262,14 @@ static ulong flash_recognize (vu_long *base)
        *sb = 0x0090;
        id = base[0];
 
-       switch (id & FLASH_VENDMASK) {
-       case (MT_MANUFACT & FLASH_VENDMASK):    /* MT or => Intel */
-       case (INTEL_ALT_MANU & FLASH_VENDMASK):
+       switch (id & 0x00FF0000)
+       {
+               case (MT_MANUFACT & 0x00FF0000):        /* MT or => Intel */
+               case (INTEL_ALT_MANU & 0x00FF0000):
                res = FLASH_MAN_INTEL;
                break;
        default:
                res = FLASH_UNKNOWN;
-               break;
        }
 
        *sb = 0xffff;
@@ -396,7 +397,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
                        if (flag)
                                enable_interrupts();
 
-                       *addr = 0x0070; /*Read status register command*/
+                       *addr = 0x70; /*Read status register command*/
                        tmp = (short)*addr & 0x00FF; /* Read the status */
                        while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
                                if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
@@ -429,7 +430,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last)
        return rcode;
 }
 
-static void flash_unprotect (flash_info_t *info)
+void flash_unprotect (flash_info_t *info)
 {
        /*We can only unprotect the whole flash at once*/
        /*Therefore we must prevent the _flash_real_protect()*/
@@ -523,7 +524,7 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int write_word (flash_info_t *info, ulong dest, ulong da)
+int write_word (flash_info_t *info, ulong dest, ulong da)
 {
        vu_short *addr = (vu_short *)dest;
        ulong start;
@@ -539,7 +540,8 @@ static int write_word (flash_info_t *info, ulong dest, ulong da)
        /* Disable interrupts which might cause a timeout here */
        flag = disable_interrupts();
 
-       for(i = 0; i < 2; i++) {
+       for(i = 0; i < 2; i++)
+       {
                /* Write Command */
                *addr = 0x0010;
 
@@ -554,7 +556,7 @@ static int write_word (flash_info_t *info, ulong dest, ulong da)
                start = get_timer (0);
                flag  = 0;
                *addr = 0x0070; /*Read statusregister command */
-               while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS) != INTEL_FLASH_STATUS_WSMS) {
+               while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
                        if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
                                flag = 1;
                                break;
@@ -577,24 +579,31 @@ static int write_word (flash_info_t *info, ulong dest, ulong da)
        return (flag);
 }
 
-int flash_real_protect(flash_info_t *info, long sector, int prot)
+int flash_real_protect(flash_info_t *info, long offset, int prot)
 {
-       int i;
+       int i, idx;
+
+       for(idx = 0; idx < info->sector_count; idx++)
+               if(info->start[idx] == offset)
+                       break;
+
+       if(idx==info->sector_count)
+               return -1;
 
        if(prot == 0) {
                /* Unprotect one sector, which means unprotect all flash
                 * and reprotect the other protected sectors.
                 */
                _flash_real_protect(info, 0, 0); /* Unprotects the whole flash*/
-               info->protect[sector] = 0;
+               info->protect[idx] = 0;
 
-               for(i = 0; i < info->sector_count; i++) {
+               for(i = 0; i < info->sector_count; i++)
                        if(info->protect[i])
                                _flash_real_protect(info, i, 1);
                }
-       } else {
+       else {
                /* We can protect individual sectors */
-               _flash_real_protect(info, sector, 1);
+               _flash_real_protect(info, idx, 1);
        }
 
        for( i = 0; i < info->sector_count; i++)
@@ -603,7 +612,7 @@ int flash_real_protect(flash_info_t *info, long sector, int prot)
        return 0;
 }
 
-static int _flash_real_protect(flash_info_t *info, long sector, int prot)
+int _flash_real_protect(flash_info_t *info, long idx, int prot)
 {
        vu_short *addr;
        int flag;
@@ -618,14 +627,15 @@ static int _flash_real_protect(flash_info_t *info, long sector, int prot)
        }
 
        if(prot == 0) {
-               /* Unlock the sector */
+               /*Unlock the sector*/
                cmd = 0x00D0;
-       } else {
-               /* Lock the sector */
+       }
+       else {
+               /*Lock the sector*/
                cmd = 0x0001;
        }
 
-       addr = (vu_short *)(info->start[sector]);
+       addr = (vu_short *)(info->start[idx]);
 
        /* If chip is busy, wait for it */
        start = get_timer(0);

diff --git a/board/ppmc8260/Makefile b/board/ppmc8260/Makefile
new file mode 100644 (file)
index 0000000..63083a4
--- /dev/null
+++ b/board/ppmc8260/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB    = lib$(BOARD).a
+
+OBJS   := ppmc8260.o strataflash.o
+
+$(LIB):        $(OBJS) $(SOBJS)
+       $(AR) crv $@ $^
+
+clean:
+       rm -f $(SOBJS) $(OBJS)
+
+distclean:     clean
+       rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:       Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+               $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################

diff --git a/board/ppmc8260/config.mk b/board/ppmc8260/config.mk
new file mode 100644 (file)
index 0000000..d06fcea
--- /dev/null
+++ b/board/ppmc8260/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2000
+# Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+# Marius Groeger <mgroeger@sysgo.de>
+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# MBX8xx boards
+#
+
+TEXT_BASE = 0xfe000000
+TEXT_END  = 0xfe080000
+PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board

diff --git a/board/ppmc8260/ppcboot.lds b/board/ppmc8260/ppcboot.lds
new file mode 100644 (file)
index 0000000..2aee65b
--- /dev/null
+++ b/board/ppmc8260/ppcboot.lds
@@ -0,0 +1,118 @@
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)          }
+  .dynsym        : { *(.dynsym)                }
+  .dynstr        : { *(.dynstr)                }
+  .rel.text      : { *(.rel.text)              }
+  .rela.text     : { *(.rela.text)     }
+  .rel.data      : { *(.rel.data)              }
+  .rela.data     : { *(.rela.data)     }
+  .rel.rodata    : { *(.rel.rodata)    }
+  .rela.rodata   : { *(.rela.rodata)   }
+  .rel.got       : { *(.rel.got)               }
+  .rela.got      : { *(.rela.got)              }
+  .rel.ctors     : { *(.rel.ctors)     }
+  .rela.ctors    : { *(.rela.ctors)    }
+  .rel.dtors     : { *(.rel.dtors)     }
+  .rela.dtors    : { *(.rela.dtors)    }
+  .rel.bss       : { *(.rel.bss)               }
+  .rela.bss      : { *(.rela.bss)              }
+  .rel.plt       : { *(.rel.plt)               }
+  .rela.plt      : { *(.rela.plt)              }
+  .init          : { *(.init)  }
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/mpc8260/start.o        (.text)
+    *(.text)
+    common/environment.o(.text)
+    *(.fixup)
+    *(.got1)
+    . = ALIGN(16);
+    *(.rodata)
+    *(.rodata1)
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x0FFF) & 0xFFFFF000;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(4096);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(4096);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  }
+  _end = . ;
+  PROVIDE (end = .);
+}
+

diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c
new file mode 100644 (file)
index 0000000..b3039fd
--- /dev/null
+++ b/board/ppmc8260/ppmc8260.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <ioports.h>
+#include <mpc8260.h>
+
+/*
+ * I/O Port configuration table
+ *
+ * if conf is 1, then that port pin will be configured at boot time
+ * according to the five values podr/pdir/ppar/psor/pdat for that entry
+ */
+
+const iop_conf_t iop_conf_tab[4][32] = {
+
+
+    /* Port A configuration */
+    {  /*            conf ppar psor pdir podr pdat */
+        /* PA31 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMTXEN */
+       /* PA30 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTCA   */
+       /* PA29 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTSOC  */
+       /* PA28 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 *ATMRXEN */
+       /* PA27 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRSOC */
+       /* PA26 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRCA */
+       /* PA25 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[0] */
+       /* PA24 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[1] */
+       /* PA23 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[2] */
+       /* PA22 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[3] */
+       /* PA21 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[4] */
+       /* PA20 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[5] */
+       /* PA19 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[6] */
+       /* PA18 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMTXD[7] */
+       /* PA17 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
+       /* PA16 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
+       /* PA15 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
+       /* PA14 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
+       /* PA13 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
+       /* PA12 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
+       /* PA11 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
+       /* PA10 */ {   0,   0,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
+       /* PA9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC2 TXD */
+       /* PA8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC2 RXD */
+       /* PA7  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_A1:L1TSYNC */
+       /* PA6  */ {   1,   0,   0,   1,   0,   0   }, /* TDN_A1:L1RSYNC */
+       /* PA5  */ {   0,   0,   0,   0,   0,   0   }, /* PA5 */
+       /* PA4  */ {   0,   0,   0,   0,   0,   0   }, /* PA4 */
+       /* PA3  */ {   0,   0,   0,   0,   0,   0   }, /* PA3 */
+       /* PA2  */ {   0,   0,   0,   0,   0,   0   }, /* PA2 */
+       /* PA1  */ {   0,   0,   0,   0,   0,   0   }, /* PA1 */
+       /* PA0  */ {   0,   0,   0,   0,   0,   0   }  /* PA0 */
+    },
+
+    /* Port B configuration */
+    {   /*           conf ppar psor pdir podr pdat */
+       /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
+       /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
+       /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
+       /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
+       /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
+       /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
+       /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
+       /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
+       /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
+       /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
+       /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
+       /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
+       /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
+       /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
+       /* PB17 */ {   0,   0,   0,   0,   0,   0   }, /* PB17 */
+       /* PB16 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_A1:L1CLK0 */
+       /* PB15 */ {   1,   0,   0,   1,   0,   1   }, /* /FETHRST */
+       /* PB14 */ {   1,   0,   0,   1,   0,   0   }, /* FETHDIS */
+       /* PB13 */ {   0,   0,   0,   0,   0,   0   }, /* PB13 */
+       /* PB12 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_B1:L1CLK0 */
+       /* PB11 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TXD */
+       /* PB10 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RXD */
+       /* PB9  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1TSYNC */
+       /* PB8  */ {   1,   0,   0,   1,   0,   0   }, /* TDM_D1:L1RSYNC */
+       /* PB7  */ {   0,   0,   0,   0,   0,   0   }, /* PB7 */
+       /* PB6  */ {   0,   0,   0,   0,   0,   0   }, /* PB6 */
+       /* PB5  */ {   0,   0,   0,   0,   0,   0   }, /* PB5 */
+       /* PB4  */ {   0,   0,   0,   0,   0,   0   }, /* PB4 */
+       /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    },
+
+    /* Port C */
+    {   /*           conf ppar psor pdir podr pdat */
+       /* PC31 */ {   0,   0,   0,   0,   0,   0   }, /* PC31 */
+       /* PC30 */ {   0,   0,   0,   0,   0,   0   }, /* PC30 */
+       /* PC29 */ {   0,   0,   0,   0,   0,   0   }, /* PC28 */
+       /* PC28 */ {   1,   1,   0,   0,   0,   0   }, /* CLK4 */
+       /* PC27 */ {   0,   0,   0,   0,   0,   0   }, /* PC27 */
+       /* PC26 */ {   0,   0,   0,   0,   0,   0   }, /* PC26 */
+       /* PC25 */ {   1,   1,   0,   0,   0,   0   }, /* CLK7 */
+       /* PC24 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+       /* PC23 */ {   1,   0,   0,   1,   0,   0   }, /* ATMTFCLK */
+       /* PC22 */ {   0,   0,   0,   0,   0,   0   }, /* PC22 */
+       /* PC21 */ {   0,   0,   0,   0,   0,   0   }, /* PC23 */
+       /* PC20 */ {   0,   0,   0,   0,   0,   0   }, /* PC24 */
+       /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK */
+       /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII TX_CLK */
+       /* PC17 */ {   0,   0,   0,   0,   0,   0   }, /* PC17 */
+       /* PC16 */ {   0,   0,   0,   0,   0,   0   }, /* PC16 */
+       /* PC15 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[0] */
+       /* PC14 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[0] */
+       /* PC13 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[1] */
+       /* PC12 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[1] */
+       /* PC11 */ {   1,   1,   0,   1,   0,   0   }, /* TDM_D1:L1CLK0 */
+       /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDC */
+       /* PC9  */ {   1,   0,   0,   1,   0,   0   }, /* FCC2 MDIO */
+       /* PC8  */ {   0,   0,   0,   0,   0,   0   }, /* PC8 */
+       /* PC7  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:TxAddr[2]*/
+       /* PC6  */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[2] */
+       /* PC5  */ {   0,   0,   0,   0,   0,   0   }, /* PC5 */
+       /* PC4  */ {   0,   0,   0,   0,   0,   0   }, /* PC4 */
+       /* PC3  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DACK */
+       /* PC2  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DONE */
+       /* PC1  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA2:DREQ */
+       /* PC0  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DREQ */
+    },
+
+    /* Port D */
+    {   /*           conf ppar psor pdir podr pdat */
+       /* PD31 */ {   0,   0,   0,   0,   0,   0   }, /* PD31 */
+       /* PD30 */ {   0,   0,   0,   0,   0,   0   }, /* PD30 */
+       /* PD29 */ {   1,   0,   0,   1,   0,   0   }, /* FCC1:RxAddr[3] */
+       /* PD28 */ {   0,   0,   0,   0,   0,   0   }, /* PD28 */
+       /* PD27 */ {   0,   0,   0,   0,   0,   0   }, /* PD27 */
+       /* PD26 */ {   1,   0,   0,   1,   0,   0   }, /* TDM_C1:L1RSYNC */
+       /* PD25 */ {   0,   0,   0,   0,   0,   0   }, /* PD25 */
+       /* PD24 */ {   0,   0,   0,   0,   0,   0   }, /* PD24 */
+       /* PD23 */ {   0,   0,   0,   0,   0,   0   }, /* PD23 */
+       /* PD22 */ {   0,   0,   0,   0,   0,   0   }, /* PD22 */
+       /* PD21 */ {   0,   0,   0,   0,   0,   0   }, /* PD21 */
+       /* PD20 */ {   0,   0,   0,   0,   0,   0   }, /* PD20 */
+       /* PD19 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+       /* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD19 */
+       /* PD17 */ {   1,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
+       /* PD16 */ {   1,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
+       /* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
+       /* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+       /* PD13 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TXD */
+       /* PD12 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RXD */
+       /* PD11 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1TSYNC */
+       /* PD10 */ {   1,   0,   0,   0,   0,   0   }, /* TDM_B1:L1RSYNC*/
+       /* PD9  */ {   1,   1,   0,   1,   0,   0   }, /* SMC1:TXD */
+       /* PD8  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:RXD */
+       /* PD7  */ {   1,   1,   0,   0,   0,   0   }, /* SMC1:SMSYN */
+       /* PD6  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DACK */
+       /* PD5  */ {   1,   0,   0,   1,   0,   0   }, /* IDMA1:DONE */
+       /* PD4  */ {   0,   0,   0,   0,   0,   0   }, /* PD4 */
+       /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
+       /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
+    }
+};
+
+/* ------------------------------------------------------------------------- */
+
+/*
+ * Check Board Identity:
+ */
+
+int checkboard(void)
+{
+    printf ("Wind River PPMC8260\n");
+
+    return 1;
+}
+
+/* ------------------------------------------------------------------------- */
+
+long int initdram(int board_type)
+{
+       volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+       volatile memctl8260_t *memctl = &immap->im_memctl;
+       volatile uchar c = 0xff;
+       volatile uchar *ramaddr0 = (uchar *)(CFG_SDRAM0_BASE);
+       volatile uchar *ramaddr1 = (uchar *)(CFG_SDRAM1_BASE);
+       ulong psdmr = CFG_PSDMR;
+       volatile uchar *ramaddr2 = (uchar *)(CFG_SDRAM2_BASE);
+       ulong lsdmr = CFG_LSDMR;
+       int i;
+       
+       /*
+        * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
+        *
+        * "At system reset, initialization software must set up the
+        *  programmable parameters in the memory controller banks registers
+        *  (ORx, BRx, P/LSDMR). After all memory parameters are configured,
+        *  system software should execute the following initialization sequence
+        *  for each SDRAM device.
+        *
+        *  1. Issue a PRECHARGE-ALL-BANKS command
+        *  2. Issue eight CBR REFRESH commands
+        *  3. Issue a MODE-SET command to initialize the mode register
+        *
+        *  The initial commands are executed by setting P/LSDMR[OP] and
+        *  accessing the SDRAM with a single-byte transaction."
+        *
+        * The appropriate BRx/ORx registers have already been set when we
+        * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+        */
+       
+       memctl->memc_psrt = CFG_PSRT;
+       memctl->memc_mptpr = CFG_MPTPR;
+
+#ifndef CFG_RAMBOOT
+       memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
+       *ramaddr0++ = c;
+       *ramaddr1++ = c;
+
+       memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
+       for (i = 0; i < 8; i++) {
+               *ramaddr0++ = c;
+               *ramaddr1++ = c;
+       }
+
+       memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
+       ramaddr0 = (uchar *)(CFG_SDRAM0_BASE + 0x110);
+       ramaddr1 = (uchar *)(CFG_SDRAM1_BASE + 0x110);
+       *ramaddr0 = c;
+       *ramaddr1 = c;
+
+       memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+       *ramaddr0 = c;
+       *ramaddr1 = c;
+
+       memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
+       *ramaddr2++ = c;
+
+       memctl->memc_lsdmr = lsdmr | PSDMR_OP_CBRR;
+       for (i = 0; i < 8; i++) {
+               *ramaddr2++ = c;
+       }
+
+       memctl->memc_lsdmr = lsdmr | PSDMR_OP_MRW;
+       *ramaddr2++ = c;
+
+       memctl->memc_lsdmr = lsdmr | PSDMR_OP_NORM | PSDMR_RFEN;
+       *ramaddr2 = c;
+#endif
+       
+       /* return total ram size */
+       return ((CFG_SDRAM0_SIZE+CFG_SDRAM1_SIZE) * 1024 * 1024);
+}
+#ifdef CONFIG_MISC_INIT_R
+/* ------------------------------------------------------------------------- */
+void misc_init_r(bd_t *bd)
+{
+#ifdef CFG_LED_BASE
+  uchar ds = *(unsigned char *)(CFG_LED_BASE + 1);
+  uchar ss;
+  uchar tmp[64];
+  int res;
+  if((ds != 0) && (ds != 0xff)) {
+    res = getenv_r("ethaddr", tmp, sizeof(tmp));
+    if(res > 0) {
+      ss = ((ds >> 4) & 0x0f);
+      ss +=  ss < 0x0a?'0':('a'- 10);
+      tmp[15] = ss;
+
+      ss = (ds & 0x0f);
+      ss +=  ss < 0x0a?'0':('a'- 10);
+      tmp[16] = ss;
+      
+      tmp[17] = '\0';
+      setenv("ethaddr", tmp);
+      /* set the led to show the address */
+      *((unsigned char *)(CFG_LED_BASE + 1)) = ds;
+    }
+  }
+#endif /* CFG_LED_BASE */
+}
+#endif /* CONFIG_MISC_INIT_R */

diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c
new file mode 100644 (file)
index 0000000..7a25cdb
--- /dev/null
+++ b/board/ppmc8260/strataflash.c
@@ -0,0 +1,650 @@
+/*
+ * (C) Copyright 2002
+ * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <ppcboot.h>
+#include <mpc8260.h>
+#include <asm/processor.h>
+
+/*
+ * This file implements a Common Flash Interface (CFI) driver for ppcboot.
+ * The width of the port and the width of the chips are determined at initialization.
+ * These widths are used to calculate the address for access CFI data structures.
+ * It has been tested on an Intel Strataflash implementation.
+ *
+ * References
+ * JEDEC Standard JESD68 - Common Flash Interface (CFI)
+ * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
+ * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
+ * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
+ * 
+ * TODO
+ * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
+ * Add support for other command sets Use the PRI and ALT to determine command set
+ * Verify erase and program timeouts.
+ */ 
+
+#define FLASH_CMD_CFI                     0x98
+#define FLASH_CMD_READ_ID                 0x90
+#define FLASH_CMD_RESET                   0xff
+#define FLASH_CMD_BLOCK_ERASE             0x20
+#define FLASH_CMD_ERASE_CONFIRM           0xD0
+#define FLASH_CMD_WRITE                   0x40
+#define FLASH_CMD_PROTECT                 0x60
+#define FLASH_CMD_PROTECT_SET             0x01
+#define FLASH_CMD_PROTECT_CLEAR           0xD0
+#define FLASH_CMD_CLEAR_STATUS            0x50
+
+#define FLASH_STATUS_DONE                 0x80
+#define FLASH_STATUS_ESS                  0x40
+#define FLASH_STATUS_ECLBS                0x20
+#define FLASH_STATUS_PSLBS                0x10
+#define FLASH_STATUS_VPENS                0x08
+#define FLASH_STATUS_PSS                  0x04
+#define FLASH_STATUS_DPS                  0x02
+#define FLASH_STATUS_R                    0x01
+#define FLASH_STATUS_PROTECT              0x01
+
+#define FLASH_OFFSET_CFI                  0x55
+#define FLASH_OFFSET_CFI_RESP             0x10
+#define FLASH_OFFSET_WTOUT                0x1F
+#define FLASH_OFFSET_ETOUT                0x21
+#define FLASH_OFFSET_WMAX_TOUT            0x23
+#define FLASH_OFFSET_EMAX_TOUT            0x25
+#define FLASH_OFFSET_SIZE                 0x27
+#define FLASH_OFFSET_NUM_ERASE_REGIONS    0x2C
+#define FLASH_OFFSET_ERASE_REGIONS        0x2D
+#define FLASH_OFFSET_PROTECT              0x02
+
+
+#define FLASH_MAN_CFI                     0x01000000
+
+
+
+
+typedef union {
+       unsigned char c;
+       unsigned short w;
+       unsigned long l;
+} cfiword_t;
+
+typedef union {
+       unsigned char * cp;
+       unsigned short *wp;
+       unsigned long *lp;
+} cfiptr_t;
+
+#define NUM_ERASE_REGIONS 4
+
+flash_info_t   flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
+
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+
+
+
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
+static int flash_detect_cfi(flash_info_t * info);
+static ulong flash_get_size (ulong base, int banknum);
+static void flash_status_display(flash_info_t * info, int sect);
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
+
+/*-----------------------------------------------------------------------
+ * create an address based on the offset and the port width
+ */
+inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
+{
+       return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
+}
+/*-----------------------------------------------------------------------
+ * read a character at a port width address
+ */
+inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
+{
+       uchar *cp;
+       cp = flash_make_addr(info, 0, offset);
+       return (cp[info->portwidth - 1]);
+}
+
+/*-----------------------------------------------------------------------
+ * read a long word by picking the least significant byte of each maiximum 
+ * port size word. Swap for ppc format.
+ */
+ulong flash_read_long(flash_info_t * info, int sect,  uchar offset)
+{
+    uchar * addr;
+
+    addr = flash_make_addr(info, sect, offset);
+    return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) | 
+           (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+unsigned long flash_init (void)
+{
+       unsigned long size;
+       int i;
+       unsigned long  address;
+       
+       
+       /* The flash is positioned back to back, with the demultiplexing of the chip
+        * based on the A24 address line.
+        * 
+        */
+       
+       address = CFG_FLASH_BASE;
+       size = 0;
+
+       
+       /* Init: no FLASHes known */
+       for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+               flash_info[i].flash_id = FLASH_UNKNOWN;
+               size += flash_info[i].size = flash_get_size(address, i);
+               address += CFG_FLASH_INCREMENT;
+               if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+                       printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
+                               flash_info[0].size, flash_info[i].size<<20);
+               }
+       }
+       
+       /* Monitor protection ON by default */
+#if (CFG_MONITOR_BASE > CFG_FLASH_BASE)
+       (void)flash_protect(FLAG_PROTECT_SET,
+                           CFG_MONITOR_BASE,
+                           CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+                           &flash_info[0]);
+#endif
+       
+       return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_erase (flash_info_t *info, int s_first, int s_last)
+{
+       int rcode = 0;
+       int prot;
+       int sect;
+
+       if( info->flash_id != FLASH_MAN_CFI) {
+               printf ("Can't erase unknown flash type - aborted\n");
+               return 1;
+       }
+       if ((s_first < 0) || (s_first > s_last)) {
+               printf ("- no sectors to erase\n");
+               return 1;
+       }
+
+       prot = 0;
+       for (sect=s_first; sect<=s_last; ++sect) {
+               if (info->protect[sect]) {
+                       prot++;
+               }
+       }
+       if (prot) {
+               printf ("- Warning: %d protected sectors will not be erased!\n",
+                       prot);
+       } else {
+               printf ("\n");
+       }
+  
+       
+       for (sect = s_first; sect<=s_last; sect++) {
+               if (info->protect[sect] == 0) { /* not protected */
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
+                       flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
+                       
+                       while(!flash_isset(info, sect, 0, FLASH_STATUS_DONE));
+                       if(!flash_isequal(info,sect, 0, FLASH_STATUS_DONE)) {
+                               flash_status_display(info, sect);
+                               rcode = 1;
+                       } else
+                               printf(".");
+               }
+               flash_write_cmd(info, sect, 0,  FLASH_CMD_RESET);
+               flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+               
+       }
+       
+       printf (" done\n");
+       return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info  (flash_info_t *info)
+{
+       int i;
+       
+       if (info->flash_id != FLASH_MAN_CFI) {
+               printf ("missing or unknown FLASH type\n");
+               return;
+       }
+
+       printf("CFI conformant FLASH (%d x %d)",
+              (info->portwidth  << 3 ), (info->chipwidth  << 3 ));
+       printf ("  Size: %ld MB in %d Sectors\n",
+               info->size >> 20, info->sector_count);
+       printf(" Erase timeout %ld ms, write timeout %ld ms\n", 
+              info->erase_blk_tout, info->write_tout);
+       
+       printf ("  Sector Start Addresses:");
+       for (i=0; i<info->sector_count; ++i) {
+               if ((i % 5) == 0)
+                       printf ("\n   ");
+               printf (" %08lX%s",
+                       info->start[i],
+                       info->protect[i] ? " (RO)" : "     "
+                       );
+       }
+       printf ("\n");
+       return;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
+{
+       ulong wp;
+       ulong cp;
+       int aln;
+       cfiword_t cword;
+       int i, rc;
+
+       /* get lower aligned address */
+       wp = (addr & ~(info->portwidth - 1));
+       
+       /* handle unaligned start */
+       if((aln = addr - wp) != 0) {
+               cword.l = 0;
+               cp = wp;
+               for(i=0;i<aln; ++i, ++cp) 
+                       flash_add_byte(info, &cword, (*(uchar *)cp));
+                       
+               for(; (i< info->portwidth) && (cnt > 0) ; i++) {
+                       flash_add_byte(info, &cword, *src++);
+                       cnt--;
+                       cp++;
+               }
+               for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
+                       flash_add_byte(info, &cword, (*(uchar *)cp));
+               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+                       return rc;
+               wp += info->portwidth;
+       }
+
+       /* handle the aligned part */
+       while(cnt >= info->portwidth) {
+               cword.l = 0;
+               for(i = 0; i < info->portwidth; i++) {
+                       flash_add_byte(info, &cword, *src++);
+               }
+               if((rc = flash_write_cfiword(info, wp, cword)) != 0)
+                       return rc;
+               wp += info->portwidth;
+               cnt -= info->portwidth;
+       }
+
+       if (cnt == 0) {
+               return (0);
+       }
+       
+       /*
+        * handle unaligned tail bytes
+        */
+       cword.l = 0;
+       for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
+               flash_add_byte(info, &cword, *src++);
+               --cnt;
+       }
+       for (; i<info->portwidth; ++i, ++cp) {
+               flash_add_byte(info, & cword, (*(uchar *)cp));
+       }
+       
+       return flash_write_cfiword(info, wp, cword);
+}
+
+/*-----------------------------------------------------------------------
+ */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+       long sectnum;
+       ulong start;
+       
+       
+       for(sectnum = 0; sectnum<info->sector_count; sectnum++)
+               if(info->start[sectnum] == sector)
+                       break;
+       
+       flash_write_cmd(info, sectnum, 0, FLASH_CMD_CLEAR_STATUS);
+       flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT);
+       if(prot)
+               flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT_SET);
+       else
+               flash_write_cmd(info, sectnum, 0, FLASH_CMD_PROTECT_CLEAR);
+       
+       /* Wait for command completion */
+       start = get_timer (0);
+       while(!flash_isset(info, sectnum, 0, FLASH_STATUS_DONE)) {
+               if (get_timer(start) > info->erase_blk_tout) {
+                       printf("Flash %sprotect timeout at address %lx\n", prot?"":"un", sector);
+                       flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
+                       return 1;
+               }
+       }
+       if(!flash_isequal(info,sectnum, 0, FLASH_STATUS_DONE)) {
+               printf("\nFlash %sprotect error at address %lx\n", prot?"":"un",sector);
+               flash_status_display(info, 0);
+               flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
+               return 1;
+       }
+       flash_write_cmd(info, sectnum, 0, FLASH_CMD_RESET);
+       info->protect[sectnum] = prot;
+       /* Intel's unprotect unprotects all locking */ 
+       if(prot == 0) {
+               int i;
+               for(i = 0 ; i<info->sector_count; i++) {
+                       if(info->protect[i])
+                               flash_real_protect(info, info->start[i], 1);
+               }
+       }
+                               
+       return 0;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
+{
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               cword->c = c;
+               break;
+       case FLASH_CFI_16BIT:
+               cword->w = (cword->w << 8) | c;
+               break;
+       case FLASH_CFI_32BIT:
+               cword->l = (cword->l << 8) | c;
+       }
+}
+
+
+/*-----------------------------------------------------------------------
+ * make a proper sized command based on the port and chip widths
+ */
+static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
+{
+       int i;
+       uchar *cp = (uchar *)cmdbuf;
+       for(i=0; i< info->portwidth; i++) 
+               *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
+}
+
+/*
+ * Write a proper sized command to the correct address 
+ */
+static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+       
+       volatile cfiptr_t addr;
+       cfiword_t cword; 
+       addr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               *addr.cp = cword.c;
+               break;
+       case FLASH_CFI_16BIT:
+               *addr.wp = cword.w;
+               break;
+       case FLASH_CFI_32BIT:
+               *addr.lp = cword.l;
+               break;
+       }
+}
+    
+/*-----------------------------------------------------------------------
+ */
+static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+       cfiptr_t cptr;
+       cfiword_t cword;
+       int retval;
+       cptr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               retval = (cptr.cp[0] == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               retval = (cptr.wp[0] == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               retval = (cptr.lp[0] == cword.l);
+               break;
+       }
+       return retval;
+}
+/*-----------------------------------------------------------------------
+ */
+static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
+{
+       cfiptr_t cptr;
+       cfiword_t cword;
+       int retval;
+       cptr.cp = flash_make_addr(info, sect, offset);
+       flash_make_cmd(info, cmd, &cword);
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               retval = ((cptr.cp[0] & cword.c) == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               retval = ((cptr.wp[0] & cword.w) == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               retval = ((cptr.lp[0] & cword.l) == cword.l);
+               break;
+       }
+       return retval;
+}      
+
+/*-----------------------------------------------------------------------
+ * detect if flash is compatible with the Common Flash Interface (CFI)
+ * http://www.jedec.org/download/search/jesd68.pdf
+ *
+*/
+static int flash_detect_cfi(flash_info_t * info)
+{
+
+       for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
+           info->portwidth <<= 1) {
+               for(info->chipwidth =FLASH_CFI_BY8;
+                   info->chipwidth <= info->portwidth;
+                   info->chipwidth <<= 1) {
+                       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+                       flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
+                       if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
+                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
+                          flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
+                               return 1;
+               }
+       }
+       return 0;
+}
+/*
+ * The following code cannot be run from FLASH!
+ * 
+ */
+static ulong flash_get_size (ulong base, int banknum)
+{
+       flash_info_t * info = &flash_info[banknum];
+       int i, j;
+       int sect_cnt;
+       unsigned long sector;
+       unsigned long tmp;
+       int size_ratio;
+       uchar num_erase_regions;
+       int  erase_region_size;
+       int  erase_region_count;
+       
+       info->start[0] = base;
+
+       if(flash_detect_cfi(info)){
+               size_ratio = info->portwidth / info->chipwidth;
+               num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
+#ifdef DEBUG_FLASH            
+               printf("found %d erase regions\n", num_erase_regions);
+#endif
+               sect_cnt = 0;
+               sector = base;
+               for(i = 0 ; i < num_erase_regions; i++) {
+                       if(i > NUM_ERASE_REGIONS) {
+                               printf("%d erase regions found, only %d used\n",
+                                      num_erase_regions, NUM_ERASE_REGIONS);
+                               break;
+                       }
+                       tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
+                       erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
+                       tmp >>= 16;
+                       erase_region_count = (tmp & 0xffff) +1;
+                       for(j = 0; j< erase_region_count; j++) {
+                               info->start[sect_cnt] = sector;
+                               sector += (erase_region_size * size_ratio);
+                               info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
+                               sect_cnt++;
+                       }
+               }
+                       
+               info->sector_count = sect_cnt;
+               /* multiply the size by the number of chips */
+               info->size = (2 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
+               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT); 
+               info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT))); 
+               tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT); 
+               info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
+               info->flash_id = FLASH_MAN_CFI;
+       }
+       
+       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+       return(info->size);
+}
+               
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_status_display(flash_info_t * info, int sect)
+{
+       if(flash_isset(info, sect, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS))
+               printf("Command Sequence Error.\n");
+       if(flash_isset(info, sect, 0, FLASH_STATUS_ECLBS))
+               printf("Block Erase Error.\n");
+       if(flash_isset(info, sect, 0, FLASH_STATUS_DPS))
+               printf("Block locked.\n");
+       if(flash_isset(info, sect, 0, FLASH_STATUS_VPENS))
+               printf("Vpp Low Error.\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
+{
+       
+       cfiptr_t ctladdr;
+       cfiptr_t cptr;
+       int flag;
+       ulong start;
+
+
+       ctladdr.cp = flash_make_addr(info, 0, 0);
+       cptr.cp = (uchar *)dest;
+
+
+       /* Check if Flash is (sufficiently) erased */
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               flag = ((cptr.cp[0] & cword.c) == cword.c);
+               break;
+       case FLASH_CFI_16BIT:
+               flag = ((cptr.wp[0] & cword.w) == cword.w);
+               break;
+       case FLASH_CFI_32BIT:
+               flag = ((cptr.lp[0] & cword.l)  == cword.l);
+               break;
+       }
+       if(!flag)
+               return 2;
+
+       /* Disable interrupts which might cause a timeout here */
+       flag = disable_interrupts();
+       
+       flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
+       flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
+
+       switch(info->portwidth) {
+       case FLASH_CFI_8BIT:
+               cptr.cp[0] = cword.c;
+               break;
+       case FLASH_CFI_16BIT:
+               cptr.wp[0] = cword.w;
+               break;
+       case FLASH_CFI_32BIT:
+               cptr.lp[0] = cword.l;
+               break;
+       }
+
+       /* re-enable interrupts if necessary */
+       if(flag)
+               enable_interrupts();
+
+       /* data polling for D7 */
+       start = get_timer (0);
+       
+       while(!flash_isset(info, 0, 0, FLASH_STATUS_DONE)) {
+               if (get_timer(start) > info->write_tout) {
+                       printf("Write timeout at address %lx\n", (unsigned long)dest);
+                       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+                       return (1);
+               }
+       }
+       
+       if(!flash_isequal(info,0, 0, FLASH_STATUS_DONE)) {
+               printf("\nFlash write error at address %lx\n",(unsigned long)dest);
+               flash_status_display(info, 0);
+               flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+               return 2;
+       }
+       flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
+       return 0;
+}

diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk
index efe70325c209e15d536c96788b2ca376c97586f8..0cd8f4414802c91be7a479919e6f3f69d14e5a9d 100644 (file)
--- a/board/sixnet/config.mk
+++ b/board/sixnet/config.mk
@@ -25,4 +25,4 @@
 # SIXNET boards
 #
 
-TEXT_BASE = 0x02800000
+TEXT_BASE = 0xF8000000

diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c
index 1449599d36cf8998d8365af74402654968848d71..432a6c9c5eea29cf907a6324ffb43b5a111e6ddb 100644 (file)
--- a/board/sixnet/flash.c
+++ b/board/sixnet/flash.c
@@ -26,21 +26,46 @@
 
 flash_info_t   flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips        */
 
+/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ *        has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+#define        FLASH_ID_MASK   0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+#define        FLASH_ID_MASK   0xFFFFFFFF
+#endif
+
+#define FPW    FLASH_PORT_WIDTH
+#define FPWV   FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
 /*-----------------------------------------------------------------------
  * Functions
  */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static void flash_get_offsets (ulong base, flash_info_t *info);
+static ulong flash_get_size(FPWV *addr, flash_info_t *info);
+static void flash_reset(flash_info_t *info);
+static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
+static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
+static void flash_get_offsets(ulong base, flash_info_t *info);
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t *info);
+#endif
 
 /*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
  */
-
 unsigned long flash_init (void)
 {
        volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
-       unsigned long size_b0, size_b1;
+       unsigned long size_b;
        int i;
 
        /* Init: no FLASHes known */
@@ -48,41 +73,29 @@ unsigned long flash_init (void)
                flash_info[i].flash_id = FLASH_UNKNOWN;
        }
 
-       /* Static FLASH Bank configuration here - FIXME XXX */
+       size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
 
-       size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
+       flash_info[0].size = size_b;
 
        if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",size_b0, size_b0<<20);
-       }
-
-       if (FLASH_BASE1_PRELIM != 0x0) {
-               size_b1 = flash_get_size((vu_long *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-               if (size_b1 > size_b0) {
-                       printf ("## ERROR: Bank 1 (0x%08lx = %ld MB) > Bank 0 (0x%08lx = %ld MB)\n",size_b1, size_b1<<20,size_b0, size_b0<<20);
-
-                       flash_info[0].flash_id  = FLASH_UNKNOWN;
-                       flash_info[1].flash_id  = FLASH_UNKNOWN;
-                       flash_info[0].sector_count      = -1;
-                       flash_info[1].sector_count      = -1;
-                       flash_info[0].size              = 0;
-                       flash_info[1].size              = 0;
-                       return (0);
-               }
-       } else {
-               size_b1 = 0;
+               printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx\n",size_b);
        }
 
-       /* Remap FLASH according to real size */
-       memctl->memc_or0 = CFG_OR0_PRELIM;
-       memctl->memc_br0 = CFG_BR0_PRELIM;
-
-       /* Re-do sizing to get full correct info */
-       size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+       /* Remap FLASH according to real size, so only at proper address */
+       memctl->memc_or0 = (memctl->memc_or0 & ~OR_AM_MSK) | ORMASK(size_b);
 
+       /* Do this again (was done already in flast_get_size), just
+        * in case we move it when remap the FLASH.
+        */
        flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
 
+#ifdef CFG_FLASH_PROTECTION
+       /* read the hardware protection status (if any) into the 
+        * protection array in flash_info.
+        */
+       flash_sync_real_protect(&flash_info[0]);
+#endif
+
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
        /* monitor protection ON by default */
        flash_protect(FLAG_PROTECT_SET,
@@ -91,32 +104,20 @@ unsigned long flash_init (void)
                      &flash_info[0]);
 #endif
 
-       if (size_b1) {
-               memctl->memc_or1 = CFG_OR1_PRELIM;
-               memctl->memc_br1 = CFG_BR1_PRELIM;
-
-               /* Re-do sizing to get full correct info */
-               size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0), &flash_info[1]);
-
-               flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
-
-               /* monitor protection ON by default */
-               flash_protect(FLAG_PROTECT_SET,
-                             CFG_MONITOR_BASE,
-                             CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
-                             &flash_info[1]);
-       } else {
-           memctl->memc_or1 = CFG_OR1_PRELIM;
-               memctl->memc_br1 = CFG_BR1_PRELIM;
-
-               flash_info[1].flash_id = FLASH_UNKNOWN;
-               flash_info[1].sector_count = -1;
-       }
+       return (size_b);
+}
 
-       flash_info[0].size = size_b0;
-       flash_info[1].size = size_b1;
+/*-----------------------------------------------------------------------
+ */
+static void flash_reset(flash_info_t *info)
+{
+       FPWV *base = (FPWV *)(info->start[0]);
 
-       return (size_b0 + size_b1);
+       /* Put FLASH back in read mode */
+       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+               *base = (FPW)0x00FF00FF;        /* Intel Read Mode */
+       else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+               *base = (FPW)0x00F000F0;        /* AMD Read Mode */
 }
 
 /*-----------------------------------------------------------------------
@@ -126,19 +127,48 @@ static void flash_get_offsets (ulong base, flash_info_t *info)
        int i;
 
        /* set up sector start address table */
-       if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
-               /* set sector offsets for uniform sector type   */
-               for (i = 0; i < info->sector_count; i++) {
-                       info->start[i] = base + (i * 0x00040000);
+       if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+           && (info->flash_id & FLASH_BTYPE)) {
+               int bootsect_size;      /* number of bytes/boot sector  */
+               int sect_size;          /* number of bytes/regular sector */
+
+               bootsect_size = 0x00002000 * (sizeof(FPW)/2);
+               sect_size =     0x00010000 * (sizeof(FPW)/2);
+
+               /* set sector offsets for bottom boot block type        */
+               for (i = 0; i < 8; ++i) {
+                       info->start[i] = base + (i * bootsect_size);
+               }
+               for (i = 8; i < info->sector_count; i++) {
+                       info->start[i] = base + ((i - 7) * sect_size);
                }
        }
+       else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD 
+                && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+               int sect_size;          /* number of bytes/sector */
+
+               sect_size = 0x00010000 * (sizeof(FPW)/2);
+
+               /* set up sector start address table (uniform sector type) */
+               for( i = 0; i < info->sector_count; i++ )
+                       info->start[i] = base + (i * sect_size);
+       }
 }
 
 /*-----------------------------------------------------------------------
  */
-void flash_print_info  (flash_info_t *info)
+
+void flash_print_info (flash_info_t *info)
 {
        int i;
+       uchar *boottype;
+       uchar *bootletter;
+       uchar *fmt;
+       uchar botbootletter[] = "B";
+       uchar topbootletter[] = "T";
+       uchar botboottype[] = "bottom boot sector";
+       uchar topboottype[] = "top boot sector";
 
        if (info->flash_id == FLASH_UNKNOWN) {
                printf ("missing or unknown FLASH type\n");
@@ -146,21 +176,68 @@ void flash_print_info  (flash_info_t *info)
        }
 
        switch (info->flash_id & FLASH_VENDMASK) {
-               case FLASH_MAN_AMD:     printf ("AMD ");                break;
-               case FLASH_MAN_FUJ:     printf ("FUJITSU ");            break;
-               case FLASH_MAN_BM:      printf ("BRIGHT MICRO ");       break;
-               default:                printf ("Unknown Vendor ");     break;
+       case FLASH_MAN_AMD:     printf ("AMD ");                break;
+       case FLASH_MAN_BM:      printf ("BRIGHT MICRO ");       break;
+       case FLASH_MAN_FUJ:     printf ("FUJITSU ");            break;
+       case FLASH_MAN_SST:     printf ("SST ");                break;
+       case FLASH_MAN_STM:     printf ("STM ");                break;
+       case FLASH_MAN_INTEL:   printf ("INTEL ");              break;
+       default:                printf ("Unknown Vendor ");     break;
+       }
+
+       /* check for top or bottom boot, if it applies */
+       if (info->flash_id & FLASH_BTYPE) {
+               boottype = botboottype;
+               bootletter = botbootletter;
+       }
+       else {
+               boottype = topboottype;
+               bootletter = topbootletter;
        }
 
        switch (info->flash_id & FLASH_TYPEMASK) {
-       case FLASH_AM040:
-               printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
+       case FLASH_AM640U:
+               fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+               break;
+        case FLASH_28F800C3B:
+        case FLASH_28F800C3T:
+               fmt = "28F800C3%s (8 Mbit, %s)\n";
+               break;
+       case FLASH_INTEL800B:
+       case FLASH_INTEL800T:
+               fmt = "28F800B3%s (8 Mbit, %s)\n";
+               break;
+        case FLASH_28F160C3B:
+        case FLASH_28F160C3T:
+               fmt = "28F160C3%s (16 Mbit, %s)\n";
+               break;
+       case FLASH_INTEL160B:
+       case FLASH_INTEL160T:
+               fmt = "28F160B3%s (16 Mbit, %s)\n";
+               break;
+        case FLASH_28F320C3B:
+        case FLASH_28F320C3T:
+               fmt = "28F320C3%s (32 Mbit, %s)\n";
+               break;
+       case FLASH_INTEL320B:
+       case FLASH_INTEL320T:
+               fmt = "28F320B3%s (32 Mbit, %s)\n";
+               break;
+        case FLASH_28F640C3B:
+        case FLASH_28F640C3T:
+               fmt = "28F640C3%s (64 Mbit, %s)\n";
+               break;
+       case FLASH_INTEL640B:
+       case FLASH_INTEL640T:
+               fmt = "28F640B3%s (64 Mbit, %s)\n";
                break;
        default:
-               printf ("Unknown Chip Type\n");
+               fmt = "Unknown Chip Type\n";
                break;
        }
 
+       printf (fmt, bootletter, boottype);
+
        printf ("  Size: %ld MB in %d Sectors\n",
                info->size >> 20,
                info->sector_count);
@@ -172,13 +249,11 @@ void flash_print_info  (flash_info_t *info)
                        printf ("\n   ");
                }
 
-               printf (" %08lX%s",
-                       info->start[i],
-                       info->protect[i] ? " (RO)" : "     "    );
+               printf (" %08lX%s", info->start[i],
+                       info->protect[i] ? " (RO)" : "     ");
        }
 
        printf ("\n");
-       return;
 }
 
 /*-----------------------------------------------------------------------
@@ -188,26 +263,27 @@ void flash_print_info  (flash_info_t *info)
  * The following code cannot be run from FLASH!
  */
 
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
+ulong flash_get_size (FPWV *addr, flash_info_t *info)
 {
-       short i;
-       uchar value;
-
        /* Write auto select command: read Manufacturer ID */
-       addr[0x0555] = 0xAAAAAAAA;
-       addr[0x02AA] = 0x55555555;
-       addr[0x0555] = 0x90909090;
 
-       value = addr[0];
+       /* Write auto select command sequence and test FLASH answer */
+       addr[0x0555] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */
+       addr[0x02AA] = (FPW)0x00550055; /* for AMD, Intel ignores this */
+       addr[0x0555] = (FPW)0x00900090; /* selects Intel or AMD */
 
-       switch (value + (value << 16)) {
-       case AMD_MANUFACT:
+       /* The manufacturer codes are only 1 byte, so just use 1 byte.
+        * This works for any bus width and any FLASH device width.
+        */
+       switch (addr[0] & 0xff) {
+
+       case (uchar)AMD_MANUFACT:
                info->flash_id = FLASH_MAN_AMD;
-       break;
+               break;
 
-       case FUJ_MANUFACT:
-               info->flash_id = FLASH_MAN_FUJ;
-       break;
+       case (uchar)INTEL_MANUFACT:
+               info->flash_id = FLASH_MAN_INTEL;
+               break;
 
        default:
                info->flash_id = FLASH_UNKNOWN;
@@ -216,50 +292,132 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
                break;
        }
 
-       value = addr[1];                        /* device ID            */
-
-       switch (value) {
-       case AMD_ID_F040B:
-               info->flash_id += FLASH_AM040;
-               info->sector_count = 8;
-               info->size = 0x00200000;
-               break;                          /* => 2 MB              */
+       /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+       if (info->flash_id != FLASH_UNKNOWN) switch (addr[1]) {
+
+       case (FPW)AMD_ID_LV640U:        /* 29LV640 and 29LV641 have same ID */
+               info->flash_id += FLASH_AM640U;
+               info->sector_count = 128;
+               info->size = 0x00800000 * (sizeof(FPW)/2);
+               break;                          /* => 8 or 16 MB        */
+
+       case (FPW)INTEL_ID_28F800C3B:
+               info->flash_id += FLASH_28F800C3B;
+               info->sector_count = 23;
+               info->size = 0x00100000 * (sizeof(FPW)/2);
+               break;                          /* => 1 or 2 MB         */
+
+       case (FPW)INTEL_ID_28F800B3B:
+               info->flash_id += FLASH_INTEL800B;
+               info->sector_count = 23;
+               info->size = 0x00100000 * (sizeof(FPW)/2);
+               break;                          /* => 1 or 2 MB         */
+
+       case (FPW)INTEL_ID_28F160C3B:
+               info->flash_id += FLASH_28F160C3B;
+               info->sector_count = 39;
+               info->size = 0x00200000 * (sizeof(FPW)/2);
+               break;                          /* => 2 or 4 MB         */
+
+       case (FPW)INTEL_ID_28F160B3B:
+               info->flash_id += FLASH_INTEL160B;
+               info->sector_count = 39;
+               info->size = 0x00200000 * (sizeof(FPW)/2);
+               break;                          /* => 2 or 4 MB         */
+
+       case (FPW)INTEL_ID_28F320C3B:
+               info->flash_id += FLASH_28F320C3B;
+               info->sector_count = 71;
+               info->size = 0x00400000 * (sizeof(FPW)/2);
+               break;                          /* => 4 or 8 MB         */
+
+       case (FPW)INTEL_ID_28F320B3B:
+               info->flash_id += FLASH_INTEL320B;
+               info->sector_count = 71;
+               info->size = 0x00400000 * (sizeof(FPW)/2);
+               break;                          /* => 4 or 8 MB         */
+
+       case (FPW)INTEL_ID_28F640C3B:
+               info->flash_id += FLASH_28F640C3B;
+               info->sector_count = 135;
+               info->size = 0x00800000 * (sizeof(FPW)/2);
+               break;                          /* => 8 or 16 MB        */
+
+       case (FPW)INTEL_ID_28F640B3B:
+               info->flash_id += FLASH_INTEL640B;
+               info->sector_count = 135;
+               info->size = 0x00800000 * (sizeof(FPW)/2);
+               break;                          /* => 8 or 16 MB        */
 
        default:
                info->flash_id = FLASH_UNKNOWN;
+               info->sector_count = 0;
+               info->size = 0;
                return (0);                     /* => no or unknown flash */
        }
 
-       flash_get_offsets ((ulong)addr, &flash_info[0]);
+       flash_get_offsets((ulong)addr, info);
+
+       /* Put FLASH back in read mode */
+       flash_reset(info);
+
+       return (info->size);
+}
 
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void flash_sync_real_protect(flash_info_t *info)
+{
+    FPWV *addr = (FPWV *)(info->start[0]);
+    FPWV *sect;
+    int i;
+
+    switch (info->flash_id & FLASH_TYPEMASK) {
+    case FLASH_28F800C3B:
+    case FLASH_28F800C3T:
+    case FLASH_28F160C3B:
+    case FLASH_28F160C3T:
+    case FLASH_28F320C3B:
+    case FLASH_28F320C3T:
+    case FLASH_28F640C3B:
+    case FLASH_28F640C3T:
        /* check for protected sectors */
+       *addr = (FPW)0x00900090;
        for (i = 0; i < info->sector_count; i++) {
-               /* read sector protection at sector address, (A7 .. A0) = 0x02 */
-               /* D0 = 1 if protected */
-               addr = (volatile unsigned long *)(info->start[i]);
-               info->protect[i] = addr[2] & 1;
+           /* read sector protection at sector address, (A7 .. A0) = 0x02.
+            * D0 = 1 for each device if protected.
+            * If at least one device is protected the sector is marked
+            * protected, but mixed protected and  unprotected devices
+            * within a sector should never happen.
+            */
+           sect = (FPWV *)(info->start[i]);
+           info->protect[i] = (sect[2] & (FPW)(0x00010001)) ? 1 : 0;
        }
 
-       /*
-        * Prevent writes to uninitialized FLASH.
-        */
-       if (info->flash_id != FLASH_UNKNOWN) {
-               addr = (volatile unsigned long *)info->start[0];
-               *addr = 0xF0F0F0F0;     /* reset bank */
-       }
+       /* Put FLASH back in read mode */
+       flash_reset(info);
+       break;
 
-       return (info->size);
+    case FLASH_AM640U:
+    default:
+       /* no hardware protect that we support */
+       break;
+    }
 }
-
+#endif
 
 /*-----------------------------------------------------------------------
  */
 
 int    flash_erase (flash_info_t *info, int s_first, int s_last)
 {
-       vu_long *addr = (vu_long*)(info->start[0]);
-       int flag, prot, sect, l_sect;
+       FPWV *addr;
+       int flag, prot, sect;
+       int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
        ulong start, now, last;
+       int rcode = 0;
 
        if ((s_first < 0) || (s_first > s_last)) {
                if (info->flash_id == FLASH_UNKNOWN) {
@@ -270,9 +428,21 @@ int        flash_erase (flash_info_t *info, int s_first, int s_last)
                return 1;
        }
 
-       if ((info->flash_id == FLASH_UNKNOWN) ||
-           (info->flash_id > FLASH_AMD_COMP)) {
-               printf ("Can't erase unknown flash type - aborted\n");
+       switch (info->flash_id & FLASH_TYPEMASK) {
+       case FLASH_INTEL800B:
+       case FLASH_INTEL160B:
+       case FLASH_INTEL320B:
+       case FLASH_INTEL640B:
+       case FLASH_28F800C3B:
+       case FLASH_28F160C3B:
+       case FLASH_28F320C3B:
+       case FLASH_28F640C3B:
+       case FLASH_AM640U:
+               break;
+       case FLASH_UNKNOWN:
+       default:
+               printf ("Can't erase unknown flash type %08lx - aborted\n",
+                       info->flash_id);
                return 1;
        }
 
@@ -290,61 +460,72 @@ int       flash_erase (flash_info_t *info, int s_first, int s_last)
                printf ("\n");
        }
 
-       l_sect = -1;
-
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
-
-       addr[0x0555] = 0xAAAAAAAA;
-       addr[0x02AA] = 0x55555555;
-       addr[0x0555] = 0x80808080;
-       addr[0x0555] = 0xAAAAAAAA;
-       addr[0x02AA] = 0x55555555;
+       start = get_timer(0);
+       last  = start;
 
        /* Start erase on unprotected sectors */
-       for (sect = s_first; sect<=s_last; sect++) {
-               if (info->protect[sect] == 0) { /* not protected */
-                       addr = (vu_long*)(info->start[sect]);
-                       addr[0] = 0x30303030;
-                       l_sect = sect;
-               }
-       }
+       for (sect = s_first; sect<=s_last && rcode == 0; sect++) {
 
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
+               if (info->protect[sect] != 0)   /* protected, skip it */
+                       continue;
 
-       /* wait at least 80us - let's wait 1 ms */
-       udelay (1000);
+               /* Disable interrupts which might cause a timeout here */
+               flag = disable_interrupts();
 
-       /*
-        * We wait for the last triggered sector
-        */
-       if (l_sect < 0)
-               goto DONE;
-
-       start = get_timer (0);
-       last  = start;
-       addr = (vu_long*)(info->start[l_sect]);
-       while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF) {
-               if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
-                       printf ("Timeout\n");
-                       return 1;
+               addr = (FPWV *)(info->start[sect]);
+               if (intel) {
+                       *addr = (FPW)0x00500050; /* clear status register */
+                       *addr = (FPW)0x00200020; /* erase setup */
+                       *addr = (FPW)0x00D000D0; /* erase confirm */
                }
-               /* show that we're waiting */
-               if ((now - last) > 1000) {      /* every second */
-                       putc ('.');
-                       last = now;
+               else {
+                       /* must be AMD style if not Intel */
+                       FPWV *base;             /* first address in bank */
+
+                       base = (FPWV *)(info->start[0]);
+                       base[0x0555] = (FPW)0x00AA00AA; /* unlock */
+                       base[0x02AA] = (FPW)0x00550055; /* unlock */
+                       base[0x0555] = (FPW)0x00800080; /* erase mode */
+                       base[0x0555] = (FPW)0x00AA00AA; /* unlock */
+                       base[0x02AA] = (FPW)0x00550055; /* unlock */
+                       *addr = (FPW)0x00300030;        /* erase sector */
+               }
+
+               /* re-enable interrupts if necessary */
+               if (flag)
+                       enable_interrupts();
+
+               /* wait at least 50us for AMD, 80us for Intel.
+                * Let's wait 1 ms.
+                */
+               udelay (1000);
+
+               while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
+                       if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+                               printf ("Timeout\n");
+
+                               if (intel) {
+                                       /* suspend erase        */
+                                       *addr = (FPW)0x00B000B0;
+                               }
+
+                               flash_reset(info);      /* reset to read mode */
+                               rcode = 1;              /* failed */
+                               break;
+                       }
+
+                       /* show that we're waiting */
+                       if ((now - last) > 1000) {      /* every second */
+                               putc ('.');
+                               last = now;
+                       }
                }
-       }
 
-DONE:
-       /* reset to read mode */
-       addr = (volatile unsigned long *)info->start[0];
-       addr[0] = 0xF0F0F0F0;   /* reset bank */
+               flash_reset(info);      /* reset to read mode   */
+       }
 
        printf (" done\n");
-       return 0;
+       return rcode;
 }
 
 /*-----------------------------------------------------------------------
@@ -353,109 +534,225 @@ DONE:
  * 1 - write timeout
  * 2 - Flash not erased
  */
-
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-       ulong cp, wp, data;
-       int i, l, rc;
+    FPW data; /* 16 or 32 bit word, matches flash bus width on MPC8XX  */
+    int bytes; /* number of bytes to program in current word           */
+    int left;  /* number of bytes left to program                      */
+    int i, res;
 
-       wp = (addr & ~3);       /* get lower word aligned address */
+    for (left = cnt, res = 0;
+        left > 0 && res == 0;
+        addr += sizeof(data), left -= sizeof(data) - bytes) {
 
-       /*
-        * handle unaligned start bytes
-        */
-       if ((l = addr - wp) != 0) {
-               data = 0;
-               for (i=0, cp=wp; i<l; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
-               for (; i<4 && cnt>0; ++i) {
-                       data = (data << 8) | *src++;
-                       --cnt;
-                       ++cp;
-               }
-               for (; cnt==0 && i<4; ++i, ++cp) {
-                       data = (data << 8) | (*(uchar *)cp);
-               }
+        bytes = addr & (sizeof(data) - 1);
+        addr &= ~(sizeof(data) - 1);
 
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp += 4;
-       }
-
-       /*
-        * handle word aligned part
+       /* combine source and destination data so can program
+        * an entire word of 16 or 32 bits
         */
-       while (cnt >= 4) {
-               data = 0;
-               for (i=0; i<4; ++i) {
-                       data = (data << 8) | *src++;
-               }
-               if ((rc = write_word(info, wp, data)) != 0) {
-                       return (rc);
-               }
-               wp  += 4;
-               cnt -= 4;
+        for (i = 0; i < sizeof(data); i++) {
+            data <<= 8;
+            if (i < bytes || i - bytes >= left )
+               data += *((uchar *)addr + i);
+           else
+               data += *src++;
        }
 
-       if (cnt == 0) {
-               return (0);
+       /* write one word to the flash */
+       switch (info->flash_id & FLASH_VENDMASK) {
+       case FLASH_MAN_AMD:
+               res = write_word_amd(info, (FPWV *)addr, data);
+               break;
+       case FLASH_MAN_INTEL:
+               res = write_word_intel(info, (FPWV *)addr, data);
+               break;
+       default:
+               /* unknown flash type, error! */
+               printf ("missing or unknown FLASH type\n");
+               res = 1;        /* not really a timeout, but gives error */
+               break;
        }
+    }
 
-       /*
-        * handle unaligned tail bytes
-        */
-       data = 0;
-       for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-               data = (data << 8) | *src++;
-               --cnt;
-       }
-       for (; i<4; ++i, ++cp) {
-               data = (data << 8) | (*(uchar *)cp);
+    return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data)
+{
+    ulong start;
+    int flag;
+    int res = 0;       /* result, assume success       */
+    FPWV *base;                /* first address in flash bank  */
+
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+       return (2);
+    }
+
+   
+    base = (FPWV *)(info->start[0]);
+
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
+
+    base[0x0555] = (FPW)0x00AA00AA;    /* unlock */
+    base[0x02AA] = (FPW)0x00550055;    /* unlock */
+    base[0x0555] = (FPW)0x00A000A0;    /* selects program mode */
+
+    *dest = data;              /* start programming the data   */
+
+    /* re-enable interrupts if necessary */
+    if (flag)
+       enable_interrupts();
+
+    start = get_timer (0);
+
+    /* data polling for D7 */
+    while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
+       if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+           *dest = (FPW)0x00F000F0;    /* reset bank */
+           res = 1;
        }
+    }
 
-       return (write_word(info, wp, data));
+    return (res);
 }
 
 /*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
  * 0 - OK
  * 1 - write timeout
  * 2 - Flash not erased
  */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
+static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data)
 {
-       vu_long *addr = (vu_long*)(info->start[0]);
-       ulong start;
-       int flag;
+    ulong start;
+    int flag;
+    int res = 0;       /* result, assume success       */
 
-       /* Check if Flash is (sufficiently) erased */
-       if ((*((vu_long *)dest) & data) != data) {
-               return (2);
-       }
-       /* Disable interrupts which might cause a timeout here */
-       flag = disable_interrupts();
+    /* Check if Flash is (sufficiently) erased */
+    if ((*dest & data) != data) {
+       return (2);
+    }
 
-       addr[0x0555] = 0xAAAAAAAA;
-       addr[0x02AA] = 0x55555555;
-       addr[0x0555] = 0xA0A0A0A0;
+    /* Disable interrupts which might cause a timeout here */
+    flag = disable_interrupts();
 
-       *((vu_long *)dest) = data;
+    *dest = (FPW)0x00500050;   /* clear status register        */
+    *dest = (FPW)0x00FF00FF;   /* make sure in read mode       */
+    *dest = (FPW)0x00400040;   /* program setup                */
 
-       /* re-enable interrupts if necessary */
-       if (flag)
-               enable_interrupts();
+    *dest = data;              /* start programming the data   */
 
-       /* data polling for D7 */
-       start = get_timer (0);
-       while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-               if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
-                       return (1);
-               }
+    /* re-enable interrupts if necessary */
+    if (flag)
+       enable_interrupts();
+
+    start = get_timer (0);
+
+    while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
+       if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+           *dest = (FPW)0x00B000B0;    /* Suspend program      */
+           res = 1;
        }
-       return (0);
+    }
+
+    if (res == 0 && (*dest & (FPW)0x00100010))
+       res = 1;        /* write failed, time out error is close enough */
+
+    *dest = (FPW)0x00500050;   /* clear status register        */
+    *dest = (FPW)0x00FF00FF;   /* make sure in read mode       */
+
+    return (res);
 }
 
+#ifdef CFG_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
+ * FIXME - pass in sector index instead of sector address, would simplify
+ * this code a bit. w7o would need changing also.
  */
+int flash_real_protect(flash_info_t *info, long sector, int prot)
+{
+    int rcode;
+    int sectindex;
+    FPWV *addr = (FPWV *)sector;
+    FPW value;
+    int i;
+
+    rcode = 1; /* assume fails */
+    for (i = 0; rcode != 0 && i < info->sector_count; i++) {
+       if (info->start[i] == sector) {
+           sectindex = i;
+           rcode = 0;  /* success so far*/
+       }
+    }
+
+    if (rcode == 0) {
+       switch (info->flash_id & FLASH_TYPEMASK) {
+       case FLASH_28F800C3B:
+       case FLASH_28F800C3T:
+       case FLASH_28F160C3B:
+       case FLASH_28F160C3T:
+       case FLASH_28F320C3B:
+       case FLASH_28F320C3T:
+       case FLASH_28F640C3B:
+       case FLASH_28F640C3T:
+           flash_reset(info);                  /* make sure in read mode */
+           *addr = (FPW)0x00600060L;           /* lock command setup */
+           if (prot)
+               *addr = (FPW)0x00010001L;       /* lock sector */
+           else
+               *addr = (FPW)0x00D000D0L;       /* unlock sector */
+           flash_reset(info);                  /* reset to read mode */
+
+           /* now see if it really is locked/unlocked as requested */
+           *addr = (FPW)0x00900090;
+           /* read sector protection at sector address, (A7 .. A0) = 0x02.
+            * D0 = 1 for each device if protected.
+            * If at least one device is protected the sector is marked
+            * protected, but return failure. Mixed protected and
+            * unprotected devices within a sector should never happen.
+            */
+           value = addr[2] & (FPW)0x00010001;
+           if (value == 0)
+               info->protect[sectindex] = 0;
+           else if (value == (FPW)0x00010001)
+               info->protect[sectindex] = 1;
+           else {
+               /* error, mixed protected and unprotected */
+               rcode = 1;
+               info->protect[sectindex] = 1;
+           }
+           if (info->protect[sectindex] != prot)
+               rcode = 1;      /* failed to protect/unprotect as requested */
+
+           /* reload all protection bits from hardware for now */
+           flash_sync_real_protect(info);
+           break;
+
+       case FLASH_AM640U:
+       default:
+           /* no hardware protect that we support */
+           info->protect[sectindex] = prot;
+           break;
+       }
+    }
+
+    return rcode;
+}
+#endif

diff --git a/board/sixnet/fpgadata.c b/board/sixnet/fpgadata.c
new file mode 100644 (file)
index 0000000..d6252fb
--- /dev/null
+++ b/board/sixnet/fpgadata.c
@@ -0,0 +1,1719 @@
+        0xff, 0x87, 0xdf, 0xa8, 0x7f, 0xff, 0xfc, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0x8f, 0x71,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xaf, 0xff, 0xf0, 0xff, 0xdf, 0xff,
+        0xf7, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xff,
+        0xdf, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xaf, 0x7f, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xdf, 0xdf, 0x83, 0x73, 0xf0, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xf8, 0xdf, 0xdf, 0xf3, 0xf0, 0xff, 0xff,
+        0x7f, 0x8f, 0x7f, 0xf0, 0xff, 0x8f, 0x7f, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0xff, 0xfa, 0xff, 0x97, 0xcb, 0xf5, 0xf0, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71,
+        0xf1, 0xff, 0xff, 0xdf, 0x7f,
+        0xff, 0x7f, 0xd7, 0xff, 0xf3, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xd7, 0x7f, 0x73, 0xff, 0xff, 0xff,
+        0x0f, 0xff, 0xf0, 0xff, 0x7f, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0x8f, 0x7f, 0xf1,
+        0xbf, 0xef, 0xf8, 0xdf, 0xff, 0xf5, 0xff, 0xff,
+        0x8f, 0xff, 0xa0, 0xff, 0xfb, 0x8f, 0x7f, 0xf1,
+        0xff, 0xdf, 0x8f, 0x75, 0x81,
+        0xff, 0xff, 0xff, 0xf7, 0x7f, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xaf, 0xff, 0xfb, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x7f,
+        0xbf, 0x2f, 0xf0, 0xba, 0xfb, 0xf8, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xaa, 0xf7, 0xfa, 0xfb, 0xbf, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0xff, 0xdf, 0xff,
+        0xff, 0xaf, 0xf7, 0xfa, 0x7f, 0xff, 0xff, 0xbf,
+        0x7f, 0xf8, 0xff, 0xdf, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xbf, 0x7f, 0xf3, 0xdf,
+        0xff, 0xaf, 0xff, 0x72, 0xdf, 0x8f, 0xf5, 0xf0,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f,
+        0x51, 0x51, 0x75, 0x75, 0xff,
+        0xff, 0xef, 0xf7, 0x7a, 0xef, 0x8f, 0xfa, 0xf0,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8f,
+        0x1f, 0x51, 0x71, 0xf5, 0xdf,
+        0xff, 0xff, 0x87, 0x8f, 0xf0, 0x70, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xa4, 0x8f, 0x0b, 0x71, 0x91,
+        0x5f, 0xf1, 0xd5, 0x3d, 0x75,
+        0xff, 0xff, 0xf7, 0xff, 0x7f, 0x8f, 0x70, 0xff,
+        0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0x8e, 0x7f,
+        0xff, 0xf1, 0xaf, 0xfd, 0x7b,
+        0xff, 0xff, 0x8f, 0x87, 0x70, 0x70, 0xef, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71, 0xf1,
+        0xff, 0xfe, 0x7f, 0x7f, 0xff,
+        0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x3f, 0x03, 0xff, 0xf0, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1, 0xff,
+        0xff, 0x8f, 0x7f, 0xb1, 0x77,
+        0xff, 0xfd, 0x87, 0xff, 0xf0, 0x8f, 0x8f, 0xf0,
+        0xf0, 0x8f, 0xff, 0xf0, 0x8f, 0x7f, 0xf1, 0x8f,
+        0x2f, 0x81, 0x7b, 0xaf, 0xbf,
+        0xff, 0x05, 0xff, 0x78, 0x7f, 0x8f, 0x8f, 0xf0,
+        0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0x8f,
+        0x7f, 0xf0, 0xbb, 0x2e, 0xbf,
+        0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xaf,
+        0x77, 0xfb, 0xff, 0xfc, 0xbf,
+        0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xef, 0xaf, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xef, 0x8f, 0x7f, 0xff, 0xff,
+        0xff, 0x87, 0xbf, 0xb8, 0x8f, 0xff, 0xf0, 0xff,
+        0xff, 0xff, 0x8f, 0xff, 0xe0, 0xef, 0xf7, 0xf7,
+        0xfd, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x87, 0xff, 0xb8, 0xff, 0x8f, 0xff, 0xf0,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0x87,
+        0x7f, 0x81, 0x7f, 0xf7, 0xff,
+        0xff, 0x87, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xdf, 0xbf, 0x77, 0x7d, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0x7f, 0xf1,
+        0xff, 0xaf, 0xff, 0xfa, 0xff, 0xff, 0xbf, 0xef,
+        0x7a, 0xcf, 0xff, 0xbf, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x0f, 0x71, 0x91, 0xff,
+        0xff, 0xa8, 0xff, 0xf2, 0xff, 0xff, 0xff, 0xff,
+        0x9f, 0xfe, 0xf1, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x7f,
+        0xff, 0x87, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xfa,
+        0xff, 0x7f, 0x7f, 0x9f, 0x7f, 0xf0, 0xff, 0x8f,
+        0x7f, 0x81, 0x0f, 0x75, 0xf1,
+        0xff, 0xea, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0x7f, 0xff, 0xff, 0x6a, 0xfd, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0x7f, 0xe5, 0x7f,
+        0xbf, 0xff, 0xfa, 0xff, 0xfc, 0xff, 0xfc, 0xff,
+        0xff, 0xaf, 0x7f, 0xf5, 0x0f, 0xef, 0x9f, 0x7f,
+        0xff, 0xff, 0xff, 0x3f, 0xf7,
+        0xbf, 0xff, 0xf8, 0xff, 0xff, 0xfe, 0xff, 0xfc,
+        0xef, 0xff, 0x0f, 0x7f, 0xf0, 0x5f, 0xff, 0x9f,
+        0xff, 0x7f, 0xd7, 0x7f, 0x85,
+        0xbf, 0xfd, 0xf8, 0xcf, 0xcd, 0xf1, 0xf0, 0xfe,
+        0x1f, 0x7f, 0xb1, 0xea, 0xba, 0xef, 0x0f, 0x5f,
+        0x71, 0xf5, 0xcf, 0x6f, 0xa5,
+        0xff, 0xff, 0x8f, 0xff, 0x90, 0xbe, 0xf0, 0xff,
+        0xd7, 0xfe, 0x5f, 0xff, 0xef, 0x7f, 0xff, 0x7f,
+        0xee, 0xff, 0xff, 0xff, 0xff,
+        0xbf, 0x87, 0xeb, 0xf8, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x7e, 0xff, 0x6f, 0xff, 0xff, 0x9f,
+        0xff, 0xd1, 0x7f, 0x75, 0xf5,
+        0xbf, 0x80, 0x88, 0x88, 0xb0, 0xf1, 0xff, 0xff,
+        0x0f, 0x7f, 0xf9, 0xfe, 0x8f, 0x0f, 0x71, 0xf1,
+        0x5f, 0xf5, 0xcf, 0x0f, 0x05,
+        0xff, 0xff, 0xcf, 0xcf, 0xb0, 0xf1, 0xdf, 0xbf,
+        0x7f, 0xfa, 0xfe, 0xff, 0x8e, 0x7f, 0x71, 0x8f,
+        0xff, 0xa1, 0x7f, 0xf1, 0xff,
+        0xbf, 0xff, 0x7b, 0xf7, 0x8f, 0xff, 0xf0, 0xff,
+        0xcf, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xef, 0x7f,
+        0xef, 0x7f, 0xd7, 0xff, 0xfb,
+        0xff, 0x7d, 0xff, 0xef, 0x9e, 0xfe, 0xf0, 0xef,
+        0xff, 0xff, 0xf7, 0x7f, 0xff, 0xee, 0xff, 0x3f,
+        0xff, 0xdb, 0xbf, 0x7f, 0xf1,
+        0xff, 0xff, 0x9f, 0xdf, 0xb1, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+        0xcf, 0xff, 0xf1, 0xff, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xef,
+        0xff, 0x0f, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+        0xff, 0xaf, 0xff, 0x8a, 0x0e,
+        0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x9f,
+        0x8f, 0x80, 0xf1, 0xf1, 0xef, 0xff, 0xff, 0xff,
+        0xfe, 0xbf, 0x8e, 0x0b, 0x71,
+        0xbf, 0xe8, 0xf8, 0xf7, 0x7f, 0xff, 0xff, 0xef,
+        0xff, 0x8f, 0x8f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+        0xfe, 0xef, 0xff, 0x8f, 0x2f,
+        0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x9f, 0x9f, 0xf1, 0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xae, 0x0f, 0x71,
+        0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xdf,
+        0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+        0xf0, 0xff, 0xef, 0xef, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x7f, 0xf0, 0xff, 0xef,
+        0x7f, 0xf8, 0xef, 0xf7, 0xff, 0xff, 0xff, 0xef,
+        0xff, 0x8f, 0xef, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8b, 0x7e,
+        0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0xff, 0x8f,
+        0xff, 0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0xff, 0xf0, 0x9f, 0xff, 0xf0, 0xfe, 0xfe,
+        0xff, 0xff, 0x8e, 0x7f, 0xf1,
+        0xff, 0xf0, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0xef, 0xe0, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0x3f, 0xef, 0xf8, 0xff, 0x8f, 0xff, 0x70, 0x9f,
+        0xff, 0xf8, 0x1f, 0xef, 0x70, 0xff, 0x8e, 0x7e,
+        0xf1, 0xff, 0xff, 0xff, 0x8e,
+        0xff, 0x82, 0x7f, 0xf8, 0xff, 0xff, 0x7f, 0xff,
+        0xff, 0xaf, 0x6f, 0x80, 0xff, 0xf1, 0xfe, 0xff,
+        0xff, 0xff, 0xfe, 0x8f, 0x5f,
+        0xff, 0x80, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x6f, 0x9f, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xaf, 0x5f,
+        0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xaf, 0x7e, 0xf1,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0x8f, 0x6f, 0x90,
+        0xf5, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xee, 0x8e,
+        0x0f, 0x11, 0x71, 0xf1, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xf7, 0xef, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xbf, 0x87, 0xf8, 0xf8, 0xff, 0xff, 0x7f, 0xff,
+        0x7f, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xfe, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xef, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xef, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0x7d, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x9f, 0x7e, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0x0f, 0x9f, 0xf0, 0x9a, 0xff, 0xf2,
+        0xff, 0xff, 0xf7, 0xff, 0x0f, 0x3f, 0xf1, 0x9b,
+        0x7f, 0xf1, 0xfe, 0xef, 0xbf,
+        0xff, 0x7f, 0x6d, 0x9a, 0xff, 0xfa, 0x8f, 0xef,
+        0x00, 0xff, 0x90, 0xff, 0xa5, 0xdf, 0x7b, 0xf5,
+        0x8f, 0x6f, 0x81, 0x7e, 0x91,
+        0xff, 0xff, 0xff, 0xff, 0x97, 0x15, 0x70, 0xe0,
+        0xff, 0x7f, 0x7f, 0xfd, 0x5f, 0x75, 0xb5, 0xcf,
+        0x7b, 0xf5, 0xff, 0xff, 0xff,
+        0x3f, 0xff, 0xfb, 0x9d, 0xf7, 0xe8, 0x9f, 0x8f,
+        0x70, 0x70, 0x77, 0x8f, 0xf5, 0xca, 0x7f, 0xf5,
+        0xff, 0xff, 0xff, 0xff, 0xce,
+        0xff, 0xfa, 0xf7, 0x9f, 0xff, 0x92, 0xfd, 0xf8,
+        0x9f, 0x9f, 0x77, 0xf0, 0x7f, 0xb1, 0xff, 0xbb,
+        0x7e, 0xf1, 0xff, 0x8f, 0x7f,
+        0xff, 0xff, 0x67, 0xff, 0x8d, 0x9f, 0xf0, 0xf0,
+        0xff, 0x7f, 0xf7, 0x7f, 0xaf, 0xbf, 0xab, 0xfb,
+        0xfb, 0xff, 0xfe, 0xff, 0xff,
+        0xff, 0x87, 0x77, 0x9e, 0xef, 0xfa, 0xff, 0xfd,
+        0x77, 0x7f, 0xf7, 0x8f, 0xff, 0xb1, 0xef, 0xfb,
+        0xff, 0xff, 0xfe, 0xef, 0xff,
+        0xff, 0xff, 0x67, 0xef, 0x85, 0x9f, 0xf2, 0xf8,
+        0x3f, 0xf7, 0xff, 0xdf, 0xef, 0xff, 0x1f, 0x7f,
+        0xf1, 0xff, 0xff, 0xf7, 0xff,
+        0xff, 0x7f, 0x07, 0x9f, 0xe2, 0xfa, 0xf7, 0xf7,
+        0xe7, 0xff, 0xff, 0xff, 0x9f, 0x1f, 0xf1, 0xa9,
+        0xff, 0xdb, 0xff, 0xff, 0xff,
+        0xff, 0x7f, 0x97, 0x7f, 0xfa, 0xff, 0xff, 0xf7,
+        0x1f, 0xff, 0xf0, 0x7f, 0xdf, 0x7f, 0xbd, 0xfe,
+        0xf3, 0xf6, 0xbf, 0xdf, 0xfb,
+        0xff, 0xf8, 0x1f, 0xff, 0x90, 0x95, 0x8a, 0x90,
+        0xf0, 0x97, 0x77, 0x70, 0x4f, 0x1f, 0x45, 0x72,
+        0xfd, 0xff, 0xff, 0xbf, 0x7f,
+        0xbf, 0x7f, 0xf0, 0xff, 0xf5, 0xf7, 0xfd, 0xff,
+        0x77, 0xff, 0x9f, 0xef, 0xf0, 0xbf, 0x7f, 0xda,
+        0xbf, 0xf6, 0xfb, 0xff, 0xaf,
+        0xff, 0xff, 0x9f, 0x7f, 0x9a, 0xff, 0x90, 0xff,
+        0xff, 0x6f, 0xff, 0xff, 0x9e, 0xff, 0x99, 0x77,
+        0xf1, 0xfe, 0xff, 0xee, 0xef,
+        0x7f, 0x7f, 0xff, 0xff, 0xe7, 0xef, 0xf7, 0x8f,
+        0xa7, 0x70, 0xe2, 0x6f, 0xef, 0xff, 0x27, 0xff,
+        0xf3, 0xff, 0xef, 0xfe, 0xfe,
+        0xff, 0xff, 0xff, 0x6f, 0xf5, 0xff, 0xff, 0xff,
+        0x7e, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb7, 0xff,
+        0xfb, 0xff, 0xff, 0xfe, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xef,
+        0xff, 0x0f, 0x1f, 0xe1, 0xf1, 0xff, 0xff, 0xff,
+        0xdf, 0xef, 0xff, 0x80, 0x0e,
+        0xff, 0xf8, 0x6f, 0xef, 0x7f, 0xff, 0xff, 0x9f,
+        0x9f, 0x88, 0xe1, 0xf1, 0xff, 0xff, 0xf7, 0xff,
+        0xde, 0x8f, 0x0e, 0x09, 0x71,
+        0xbf, 0xe8, 0xf8, 0xf7, 0x77, 0xff, 0xff, 0xff,
+        0xff, 0x9f, 0x9f, 0xf1, 0xe1, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0xff, 0x9f, 0x3f,
+        0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x9f, 0x9f, 0xf9, 0xf9, 0xff, 0xff, 0xef, 0xff,
+        0xff, 0xff, 0xbe, 0x0f, 0x61,
+        0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0xef, 0xff,
+        0xff, 0xd7, 0xff, 0xff, 0xdf,
+        0xff, 0xf3, 0x6f, 0xfb, 0xef, 0xff, 0x8f, 0xff,
+        0xe0, 0xff, 0xff, 0xef, 0xf7, 0xf7, 0xef, 0xff,
+        0x8f, 0x77, 0xe8, 0xff, 0xef,
+        0x7f, 0xf8, 0xff, 0xf7, 0xef, 0xff, 0xff, 0xef,
+        0xff, 0x8f, 0xff, 0xe0, 0xe7, 0xff, 0xef, 0xff,
+        0xdf, 0xcf, 0xff, 0x81, 0x7e,
+        0xbf, 0xff, 0x78, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0xef, 0x9f, 0xff, 0xf0, 0xff, 0xef, 0xff,
+        0xff, 0xd7, 0xfe, 0xff, 0x8f,
+        0xff, 0x0f, 0xff, 0xf0, 0xff, 0x7f, 0x7f, 0xff,
+        0x9f, 0xff, 0xe0, 0x9f, 0xff, 0xf8, 0xff, 0xff,
+        0xff, 0xf7, 0x8e, 0x6f, 0xf1,
+        0xff, 0xf8, 0xff, 0xff, 0xff, 0x7f, 0xff, 0xff,
+        0xff, 0x8f, 0xff, 0xf0, 0xf7, 0xf7, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0x8e, 0x6f,
+        0x3f, 0xe7, 0xfc, 0xff, 0x8f, 0x7f, 0xf0, 0xcf,
+        0xef, 0xfc, 0x1f, 0xef, 0x78, 0xf7, 0x8f, 0x7e,
+        0xf1, 0xff, 0xff, 0xcf, 0x96,
+        0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xef, 0x8f, 0x7f, 0x80, 0xf7, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0x9f, 0x7f,
+        0xff, 0x80, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0x8f, 0xf7, 0x99, 0x7f, 0xf0, 0xff, 0xfe,
+        0xff, 0xff, 0xcf, 0xbf, 0x7f,
+        0xff, 0x77, 0xef, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0x0f, 0x7f, 0xf0, 0xff, 0xef, 0xff, 0xef, 0xff,
+        0xff, 0xf7, 0xb7, 0x7e, 0xf1,
+        0xff, 0xff, 0xef, 0xf7, 0xef, 0x0f, 0x8f, 0x90,
+        0xf7, 0xe0, 0xff, 0xff, 0xef, 0xff, 0xef, 0x8e,
+        0x4f, 0x99, 0x71, 0xe1, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+        0xff, 0xf7, 0xff, 0xff, 0xff,
+        0xbf, 0x87, 0xe8, 0xf8, 0xff, 0x7f, 0xf7, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xff, 0xef,
+        0x7f, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xdf,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xde,
+        0xe7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0x7f, 0xef, 0xff, 0x9f, 0xff,
+        0xf7, 0xff, 0xff, 0xff, 0xef, 0xff, 0xef, 0xff,
+        0xf7, 0xde, 0xf1, 0xff, 0xff,
+        0xff, 0xf7, 0x8f, 0xbf, 0xe8, 0x88, 0xff, 0xf8,
+        0xff, 0xff, 0xd7, 0xff, 0x2f, 0x3f, 0x51, 0x9b,
+        0x7f, 0xf1, 0xfe, 0xff, 0xdf,
+        0xff, 0x7f, 0xbf, 0xc7, 0xff, 0xf8, 0x0f, 0xff,
+        0x00, 0xff, 0xb0, 0x7f, 0x7f, 0xa7, 0x7b, 0xf5,
+        0x8f, 0x6f, 0x81, 0x7e, 0xb1,
+        0xff, 0xff, 0xdf, 0xff, 0xaf, 0x5f, 0x70, 0xf0,
+        0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0x85, 0x0f,
+        0x7b, 0xdd, 0xff, 0xff, 0xef,
+        0x7f, 0xff, 0xf9, 0x5f, 0xe7, 0xe8, 0xff, 0xef,
+        0xe8, 0xe8, 0xf7, 0xff, 0xd1, 0xaf, 0x4f, 0xfd,
+        0xbf, 0x1f, 0x7f, 0xff, 0xce,
+        0xff, 0xe8, 0xf7, 0x3f, 0xff, 0x90, 0xff, 0xf8,
+        0xff, 0x8f, 0x77, 0xb0, 0x7f, 0xb7, 0x7f, 0xbb,
+        0x7e, 0xf1, 0xbf, 0x9f, 0x7f,
+        0xff, 0xff, 0x2f, 0xbf, 0xb7, 0xff, 0xd0, 0xf0,
+        0xff, 0xff, 0xfb, 0x6f, 0x4f, 0xfb, 0x9b, 0x3b,
+        0x7b, 0xff, 0xfe, 0x7f, 0xef,
+        0xff, 0x9f, 0x73, 0xbc, 0xf7, 0xe8, 0xf7, 0xff,
+        0xbe, 0xff, 0xdb, 0xff, 0xde, 0xb9, 0x6f, 0xdb,
+        0xbf, 0xff, 0xbf, 0xff, 0xdb,
+        0xbf, 0xff, 0xf4, 0xef, 0xaf, 0xd7, 0xf0, 0xdc,
+        0xff, 0xff, 0xbf, 0xff, 0xf9, 0xdf, 0xdf, 0x7f,
+        0xf1, 0xbf, 0xef, 0xff, 0xbf,
+        0xff, 0xef, 0x87, 0xbf, 0xf0, 0xf8, 0xff, 0xfb,
+        0xfb, 0xff, 0xdf, 0xf7, 0x8f, 0x7f, 0x21, 0xb1,
+        0xff, 0x7b, 0xff, 0xff, 0xef,
+        0xff, 0xff, 0xc7, 0xff, 0xb8, 0xff, 0xf7, 0xff,
+        0x9f, 0xff, 0xf8, 0xff, 0xd7, 0x7f, 0xf5, 0xfe,
+        0xfb, 0xff, 0x8f, 0x7f, 0xf9,
+        0xff, 0xf8, 0x5f, 0xaf, 0xd0, 0xf3, 0x68, 0xf8,
+        0xf8, 0x8f, 0x6f, 0x70, 0xaf, 0x4f, 0xb5, 0x12,
+        0x05, 0x7f, 0x9f, 0xe7, 0x7f,
+        0xbf, 0x7f, 0xf0, 0xb7, 0xf7, 0xe7, 0x3b, 0xff,
+        0xfb, 0xff, 0x9f, 0x7f, 0xe0, 0xff, 0xdf, 0xe2,
+        0xbf, 0xfe, 0xf3, 0xef, 0x8f,
+        0xff, 0xff, 0xff, 0xff, 0xa0, 0xff, 0xf0, 0xff,
+        0xff, 0xff, 0xef, 0xef, 0xbf, 0x7f, 0x89, 0x7f,
+        0xd1, 0x9e, 0xff, 0xfe, 0xff,
+        0x7f, 0xfb, 0x9b, 0xef, 0x9f, 0xff, 0xd7, 0xff,
+        0xff, 0xf0, 0xfb, 0x7f, 0xff, 0xdf, 0xaf, 0xe7,
+        0xf3, 0xe7, 0x7f, 0x7f, 0xf6,
+        0xff, 0xff, 0xbf, 0xf3, 0xff, 0xf7, 0xef, 0xff,
+        0xde, 0xff, 0xff, 0xff, 0xef, 0xbf, 0xef, 0xf7,
+        0xeb, 0xff, 0xff, 0xfe, 0xff,
+        0x3f, 0x68, 0xf8, 0xf7, 0xff, 0xbf, 0xff, 0xcf,
+        0xfb, 0x0f, 0x1f, 0xe1, 0xf9, 0xf7, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x88, 0x2e,
+        0xff, 0xf8, 0x5b, 0xff, 0x7f, 0xf7, 0x7f, 0x9b,
+        0x9f, 0x88, 0xf9, 0xe1, 0xf7, 0xff, 0xff, 0xff,
+        0xfe, 0xef, 0x2e, 0x09, 0x59,
+        0xbf, 0xe8, 0xf8, 0xff, 0x7f, 0xff, 0x77, 0xff,
+        0xff, 0x87, 0xef, 0x91, 0xf9, 0xf7, 0xff, 0xff,
+        0xfe, 0xdf, 0xbf, 0x8f, 0x6f,
+        0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xf7, 0xff,
+        0xff, 0x8f, 0xe9, 0xf1, 0xff, 0xff, 0xdf, 0xf7,
+        0xff, 0xff, 0xfe, 0x2f, 0x61,
+        0xff, 0xf7, 0xff, 0xf3, 0xe7, 0xbf, 0xf7, 0xff,
+        0xff, 0xfb, 0x9f, 0xdf, 0xf7, 0xff, 0xf7, 0xbf,
+        0xff, 0xf7, 0xff, 0xff, 0xbf,
+        0xff, 0xd3, 0x7b, 0xfb, 0xf7, 0x7f, 0xc7, 0xff,
+        0xf0, 0xdf, 0xdf, 0xdf, 0xbf, 0xff, 0xff, 0xbf,
+        0xcf, 0x7f, 0xa0, 0xff, 0xef,
+        0x7f, 0xe8, 0xff, 0xf7, 0xf7, 0xff, 0xf7, 0xcf,
+        0xff, 0x8f, 0xff, 0xa0, 0xff, 0xf7, 0xef, 0xff,
+        0xff, 0xcf, 0xff, 0x81, 0x7e,
+        0xbf, 0xff, 0x78, 0xff, 0xf7, 0xbf, 0xf7, 0xff,
+        0xfb, 0xab, 0xdf, 0xe7, 0xf8, 0xf7, 0xff, 0xbf,
+        0xff, 0xff, 0xfe, 0xdf, 0xaf,
+        0xff, 0x9f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xfb,
+        0x8f, 0xff, 0xb0, 0xa7, 0xff, 0xf8, 0xff, 0xbf,
+        0xff, 0xff, 0xae, 0x7f, 0xd1,
+        0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfb,
+        0xfb, 0xaf, 0xff, 0xd8, 0xff, 0xff, 0xff, 0xff,
+        0xbf, 0xff, 0xff, 0xdf, 0x7f,
+        0x3f, 0x97, 0xf8, 0xff, 0x8f, 0x7f, 0xf0, 0xeb,
+        0xbf, 0xfc, 0x6f, 0x9f, 0x78, 0xf7, 0x8f, 0x7e,
+        0xb1, 0xff, 0x5f, 0xe5, 0x7e,
+        0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xdf, 0xaf, 0x37, 0x90, 0xff, 0xf9, 0xff, 0xff,
+        0xff, 0xff, 0xbe, 0x8f, 0x7f,
+        0xff, 0x90, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7b, 0xdf, 0xbf, 0x99, 0x7f, 0xf8, 0xff, 0xfe,
+        0xff, 0xff, 0xdf, 0xbf, 0x6f,
+        0xff, 0x7f, 0xff, 0xff, 0xdf, 0xff, 0xb7, 0xfb,
+        0xff, 0x7b, 0xf8, 0xff, 0x9f, 0xff, 0xbf, 0xbf,
+        0xf7, 0xff, 0x97, 0x7e, 0xf9,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0x87, 0x80,
+        0xf3, 0xf8, 0xff, 0xff, 0x9f, 0xf7, 0xbf, 0xce,
+        0x0f, 0xa9, 0x71, 0xf1, 0xff,
+        0xff, 0xfb, 0xbf, 0xff, 0xff, 0xff, 0xb7, 0xff,
+        0xbf, 0x3f, 0xf3, 0xff, 0xbf, 0xff, 0xbf, 0xfe,
+        0xf7, 0xff, 0xff, 0xff, 0xf7,
+        0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xf7, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xb0, 0xf0, 0xbf, 0xff,
+        0xff, 0xf7, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xef, 0xff, 0xf7, 0xff, 0xf7, 0xff,
+        0x7f, 0x7f, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xf7, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xaf, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xfe,
+        0xbf, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x77, 0xff, 0x87, 0xff,
+        0xf7, 0xfb, 0xff, 0xff, 0x9f, 0xff, 0xbf, 0xff,
+        0xcf, 0xfe, 0xf1, 0xff, 0xff,
+        0x7f, 0xf7, 0x2f, 0xdb, 0x74, 0x9c, 0xef, 0xfc,
+        0xef, 0xff, 0xff, 0xff, 0x0f, 0x2f, 0x71, 0xa3,
+        0x5f, 0xf1, 0xfe, 0xff, 0xf7,
+        0xff, 0xf7, 0x7f, 0x34, 0xff, 0xf4, 0x8f, 0xff,
+        0x00, 0xff, 0xa0, 0x5f, 0xb7, 0xdf, 0x7b, 0xfd,
+        0x8f, 0x7f, 0x81, 0x5e, 0xf1,
+        0xff, 0xff, 0xbf, 0xef, 0xef, 0x2f, 0x78, 0xf8,
+        0xff, 0xff, 0x77, 0xfb, 0xff, 0xe9, 0xad, 0x47,
+        0x73, 0xf5, 0xff, 0xff, 0xff,
+        0x7f, 0x9f, 0xef, 0xbf, 0xfb, 0xac, 0xeb, 0xdf,
+        0x60, 0xf8, 0xff, 0x0f, 0xd9, 0xe6, 0x67, 0xfd,
+        0xdf, 0x7e, 0x7f, 0xf7, 0xc6,
+        0xff, 0xec, 0xf7, 0xe7, 0x7f, 0x9c, 0xff, 0xf8,
+        0xf7, 0x8f, 0x7c, 0xb0, 0x7f, 0xff, 0x3f, 0xa3,
+        0x7e, 0xf9, 0xf7, 0x2f, 0x7f,
+        0xff, 0xfb, 0x8f, 0x9f, 0x83, 0xff, 0xb8, 0xb8,
+        0xfd, 0xff, 0xff, 0xff, 0x8f, 0xef, 0xe3, 0x73,
+        0x73, 0xef, 0xfe, 0xff, 0xff,
+        0xff, 0x9f, 0xd7, 0xf8, 0xfb, 0xec, 0xf3, 0xff,
+        0xdd, 0xff, 0xbb, 0xcf, 0xf6, 0xf9, 0x1f, 0xfb,
+        0xef, 0xdf, 0xfe, 0xdf, 0xfb,
+        0xbf, 0xff, 0xa4, 0xff, 0xff, 0xff, 0xf0, 0xfc,
+        0x7f, 0xfb, 0xde, 0xff, 0xe9, 0xbf, 0xa7, 0x3f,
+        0xf9, 0x9d, 0xef, 0xff, 0x8d,
+        0xff, 0xff, 0x87, 0xff, 0xe0, 0xfc, 0xf7, 0xfb,
+        0xfb, 0xff, 0xff, 0xef, 0x9f, 0x7f, 0x51, 0xf9,
+        0xff, 0x7b, 0xdf, 0x9f, 0xff,
+        0xff, 0xff, 0x9b, 0xf7, 0xf8, 0xff, 0xff, 0xb3,
+        0x3f, 0xd7, 0xf8, 0xe7, 0xff, 0x7f, 0xbd, 0xef,
+        0xd3, 0x9f, 0xff, 0x77, 0xf9,
+        0xff, 0xfc, 0x2f, 0xef, 0xbc, 0xeb, 0x3c, 0xd8,
+        0xd8, 0x28, 0x3f, 0x78, 0x8b, 0x0f, 0xc5, 0x63,
+        0x6d, 0x7f, 0xff, 0x9f, 0xff,
+        0xbf, 0x7f, 0xe0, 0xef, 0xff, 0xff, 0xdf, 0xdb,
+        0xeb, 0xff, 0x9f, 0x7f, 0xb8, 0xbf, 0xc7, 0xf3,
+        0xff, 0xff, 0xfb, 0xef, 0x8f,
+        0xff, 0xff, 0xaf, 0xf7, 0xac, 0xef, 0xe4, 0xff,
+        0xd1, 0xff, 0xf7, 0xf7, 0xde, 0x7f, 0xd9, 0x7f,
+        0xf1, 0xef, 0x7f, 0xff, 0xdf,
+        0x7f, 0xff, 0xdf, 0xff, 0xd7, 0xcf, 0xf3, 0xb7,
+        0xef, 0xf8, 0xf3, 0x7f, 0xb7, 0xff, 0xbf, 0xf7,
+        0xfb, 0xbf, 0xef, 0x77, 0xfe,
+        0xff, 0xf7, 0xff, 0xff, 0xf7, 0xfb, 0xef, 0xff,
+        0xb7, 0xff, 0xfb, 0xbf, 0xff, 0xff, 0xff, 0xff,
+        0xcb, 0x7f, 0xcf, 0xff, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xaf,
+        0xff, 0x0f, 0x4f, 0xb1, 0xf9, 0xf7, 0xff, 0xff,
+        0xef, 0xef, 0xff, 0x8e, 0x0e,
+        0xff, 0xf8, 0x6f, 0xff, 0x7f, 0xff, 0xff, 0xff,
+        0xdf, 0x88, 0xe9, 0xb1, 0xf7, 0xff, 0xff, 0xf7,
+        0xfe, 0xef, 0x0e, 0x09, 0x71,
+        0xff, 0xf8, 0xf8, 0xff, 0x6f, 0xef, 0xff, 0xff,
+        0xff, 0x8f, 0xaf, 0xd1, 0xf9, 0xf7, 0xbf, 0xdf,
+        0xee, 0xb7, 0xdf, 0xdf, 0xff,
+        0xbf, 0xf8, 0x6f, 0xef, 0xf7, 0xff, 0xff, 0xff,
+        0xaf, 0x8f, 0xf9, 0xf1, 0xdf, 0xdf, 0xbf, 0xf7,
+        0xdf, 0xff, 0xf6, 0xaf, 0x21,
+        0xff, 0xef, 0xef, 0xf3, 0xff, 0x2f, 0xef, 0xef,
+        0xff, 0xcf, 0xdf, 0x8f, 0xf7, 0xf7, 0xfe, 0xde,
+        0xff, 0xc7, 0xff, 0xff, 0xf7,
+        0xff, 0xcb, 0x7f, 0xfb, 0xef, 0xbf, 0xdf, 0xef,
+        0xa0, 0xdf, 0xb7, 0x8f, 0xf7, 0xf7, 0xbf, 0xff,
+        0x8f, 0x7f, 0xd0, 0xff, 0xdf,
+        0x7f, 0xf8, 0xef, 0xf7, 0xaf, 0xff, 0xff, 0x8f,
+        0xff, 0x97, 0xff, 0xb0, 0xff, 0xff, 0xbf, 0xff,
+        0xff, 0xbf, 0xff, 0x97, 0x3e,
+        0xbf, 0xff, 0x48, 0xff, 0xef, 0xbf, 0xff, 0xff,
+        0xef, 0xaf, 0xdf, 0xbf, 0xf0, 0xff, 0xbf, 0xff,
+        0xcf, 0xef, 0xee, 0xef, 0x9f,
+        0xff, 0x13, 0xff, 0xf4, 0xff, 0xaf, 0xff, 0xff,
+        0xcf, 0xdf, 0xf4, 0xff, 0xff, 0xfc, 0xff, 0xcf,
+        0xff, 0xf7, 0x8e, 0x7f, 0xf1,
+        0xff, 0xec, 0xff, 0xff, 0xff, 0xef, 0xef, 0xff,
+        0xff, 0x8f, 0xff, 0xe8, 0xfb, 0xf7, 0xff, 0xcf,
+        0xef, 0xf7, 0xf7, 0xaf, 0x3f,
+        0x3f, 0x87, 0x7c, 0xff, 0x8f, 0x7f, 0xe0, 0xdf,
+        0xcf, 0xde, 0x3f, 0xd7, 0x7c, 0xf7, 0x8f, 0x6e,
+        0xf1, 0xdf, 0x77, 0xcd, 0x6e,
+        0xff, 0x84, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xff, 0x9f, 0x7f, 0x80, 0xff, 0xf9, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0xaf, 0x3f,
+        0xbf, 0x84, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x5f, 0xef, 0xbf, 0xc9, 0x7f, 0xf0, 0xff, 0xfe,
+        0xef, 0xff, 0xef, 0xff, 0x97,
+        0xff, 0x7f, 0xcf, 0xff, 0xaf, 0xaf, 0xff, 0xff,
+        0xef, 0x7f, 0xf8, 0xff, 0xff, 0xff, 0xd7, 0xcf,
+        0xc7, 0xe7, 0xe7, 0x1e, 0xf1,
+        0xff, 0xff, 0xaf, 0xf7, 0xef, 0x5f, 0x8f, 0x80,
+        0xf0, 0xf8, 0xff, 0xbf, 0xff, 0xff, 0xd7, 0xae,
+        0x07, 0x49, 0x76, 0xd1, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xe7, 0xff, 0xff, 0xff,
+        0xaf, 0xff, 0xff, 0xf7, 0xdf, 0xff, 0xdf, 0xde,
+        0xe7, 0xff, 0xff, 0xdf, 0xff,
+        0xbf, 0x87, 0xe8, 0xf8, 0xef, 0x7f, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xd7, 0xff,
+        0xf6, 0xf7, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0xfb, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd7, 0xef,
+        0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xeb, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x97, 0xee,
+        0xf6, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xef, 0xff, 0xef, 0xff,
+        0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xdf, 0xfe,
+        0xd7, 0xff, 0xf7, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xef, 0xff, 0x9f, 0xff,
+        0xf5, 0x7f, 0xff, 0xff, 0xdf, 0xff, 0xd7, 0xff,
+        0xb6, 0x6e, 0xff, 0xff, 0xff,
+        0xff, 0xdf, 0x2f, 0xdf, 0xb8, 0x8d, 0xef, 0xf4,
+        0xdf, 0xff, 0xff, 0xff, 0x0f, 0x5f, 0xf1, 0xd1,
+        0x7f, 0xf1, 0xfe, 0xff, 0xf7,
+        0xff, 0x77, 0x6d, 0xb7, 0xfd, 0xfe, 0x8f, 0xff,
+        0x00, 0xff, 0xf0, 0x7f, 0x7d, 0xb6, 0x7f, 0xb1,
+        0x8e, 0x7e, 0x80, 0x5e, 0xb1,
+        0xff, 0xf7, 0xef, 0xf8, 0x06, 0x0b, 0x60, 0xe2,
+        0xff, 0x7f, 0x7f, 0x8b, 0xff, 0x49, 0xaf, 0x8f,
+        0x68, 0xf0, 0xbf, 0xed, 0xff,
+        0x7f, 0xbf, 0xca, 0x7f, 0xb7, 0x9b, 0xd7, 0xbf,
+        0x5f, 0xdf, 0xff, 0xeb, 0xd3, 0xaf, 0x37, 0xf9,
+        0xef, 0xf7, 0xf9, 0xb9, 0xf6,
+        0xff, 0xdc, 0xb7, 0x43, 0xfe, 0xbd, 0xfa, 0xe8,
+        0xff, 0x9b, 0x5f, 0xf2, 0x7f, 0xff, 0xef, 0xe9,
+        0x5e, 0xfb, 0xff, 0xaf, 0x6f,
+        0xff, 0xfb, 0x0d, 0xbf, 0xa9, 0xf9, 0xb1, 0xff,
+        0xe7, 0xe7, 0xbf, 0x7f, 0x0e, 0xff, 0x8f, 0xef,
+        0xf1, 0xd9, 0xff, 0xdf, 0xff,
+        0xbf, 0xee, 0x37, 0xfc, 0xe3, 0xdd, 0xef, 0xbf,
+        0x6b, 0x7f, 0xdd, 0xaf, 0x9e, 0xf1, 0x9f, 0xe9,
+        0xff, 0xff, 0xff, 0xff, 0xfb,
+        0xff, 0xff, 0x62, 0xbf, 0x8f, 0xbe, 0xf4, 0xfe,
+        0x2f, 0xff, 0xeb, 0xff, 0xe1, 0xdf, 0x17, 0x7f,
+        0x73, 0xfd, 0xff, 0xfb, 0xad,
+        0xff, 0x7f, 0x07, 0xdf, 0xf4, 0xe5, 0xde, 0xf5,
+        0xfb, 0xff, 0xfe, 0xdf, 0xbf, 0x7f, 0xf3, 0xe3,
+        0xff, 0xfb, 0xff, 0x7f, 0xff,
+        0xff, 0x7f, 0xbf, 0x77, 0xc7, 0xef, 0xfd, 0xdf,
+        0x7f, 0xbf, 0xf8, 0xff, 0xb7, 0x7f, 0xfb, 0xbf,
+        0xf7, 0xff, 0xec, 0x7f, 0xf9,
+        0xff, 0xf0, 0x0b, 0xcf, 0xa2, 0xf1, 0xf6, 0xb7,
+        0xb3, 0xeb, 0x7a, 0x6c, 0x8f, 0x0f, 0x31, 0x77,
+        0xe9, 0xf9, 0xf9, 0xed, 0x75,
+        0xbf, 0x7f, 0xd0, 0xdf, 0xeb, 0xfd, 0xf3, 0xbf,
+        0x7d, 0xff, 0xd7, 0x7b, 0xe0, 0xf7, 0x46, 0xb7,
+        0xff, 0xff, 0x7b, 0xff, 0xbf,
+        0xff, 0xff, 0xcb, 0x7f, 0x87, 0xff, 0xf0, 0xff,
+        0xff, 0x77, 0xff, 0xff, 0xbf, 0xdf, 0x81, 0x7f,
+        0xf1, 0x9e, 0xbf, 0x9e, 0xbf,
+        0x7f, 0x7f, 0xef, 0xbf, 0xef, 0xfd, 0xee, 0xdf,
+        0xef, 0x6f, 0xfb, 0x7f, 0xff, 0xdf, 0x1f, 0x9f,
+        0xf7, 0xff, 0x8f, 0xf9, 0xde,
+        0xff, 0xfd, 0xff, 0x7f, 0xfa, 0xfe, 0xcf, 0xff,
+        0x7f, 0xdf, 0xff, 0xff, 0xef, 0xbf, 0xdf, 0xff,
+        0xf7, 0xff, 0xff, 0xff, 0xff,
+        0x3f, 0x79, 0xb9, 0xf7, 0xff, 0xff, 0xff, 0xef,
+        0xf6, 0x0d, 0x0f, 0xf1, 0xf9, 0xf7, 0xfd, 0xff,
+        0xff, 0x9f, 0xed, 0x86, 0x1e,
+        0xff, 0xf1, 0x7f, 0xff, 0x7e, 0xfa, 0xff, 0xf7,
+        0x8e, 0x85, 0xf9, 0xf1, 0xf7, 0xff, 0xff, 0xff,
+        0xfe, 0xaf, 0x1c, 0x0b, 0x73,
+        0xbf, 0xc8, 0xe9, 0xff, 0x7f, 0xff, 0xff, 0xbf,
+        0xff, 0xcf, 0xef, 0xd1, 0xd1, 0xff, 0xdd, 0xff,
+        0xfe, 0xff, 0xff, 0x8f, 0x6d,
+        0xff, 0xf9, 0x7b, 0xff, 0xdf, 0xff, 0xfb, 0xff,
+        0xaf, 0x8f, 0xf9, 0xf9, 0xdf, 0xff, 0xdf, 0xff,
+        0xff, 0xff, 0xee, 0xcf, 0xdb,
+        0xff, 0xde, 0xff, 0xf6, 0xfe, 0xdf, 0x7a, 0xfe,
+        0xdf, 0xa2, 0xde, 0x8b, 0xff, 0xf2, 0xff, 0xbf,
+        0xff, 0xff, 0xff, 0xfd, 0xff,
+        0xff, 0xcf, 0x7f, 0xfe, 0xff, 0xdf, 0xaf, 0xff,
+        0xe5, 0xfa, 0xf7, 0xae, 0xd7, 0xf2, 0xff, 0xbf,
+        0xed, 0x7f, 0xb2, 0xfd, 0xbf,
+        0x7f, 0xf8, 0xfe, 0xf7, 0xff, 0x7f, 0x7f, 0xdf,
+        0xf7, 0x89, 0xbf, 0xf0, 0xdb, 0xf7, 0x97, 0xff,
+        0xff, 0x9f, 0x7f, 0x97, 0x5e,
+        0xbf, 0xff, 0x78, 0xff, 0xff, 0xdf, 0x7b, 0xfe,
+        0xff, 0xf6, 0x8f, 0xf7, 0xf8, 0xff, 0xd7, 0xbf,
+        0xfd, 0xff, 0xfe, 0xfd, 0x9f,
+        0xff, 0xa7, 0x7f, 0xf5, 0xff, 0xdf, 0xff, 0xf7,
+        0xdf, 0xff, 0xf3, 0xff, 0xf7, 0xfb, 0xff, 0x9f,
+        0xff, 0xff, 0x8e, 0x7f, 0xf3,
+        0xff, 0xd8, 0xfe, 0xfb, 0xff, 0xff, 0xdf, 0xf7,
+        0xf6, 0x8e, 0xbf, 0xd8, 0xff, 0xf7, 0xff, 0xff,
+        0xcf, 0xff, 0xff, 0xcd, 0x5f,
+        0x3f, 0x8f, 0xfd, 0xff, 0x8f, 0x5f, 0xd0, 0xf7,
+        0xd6, 0xb5, 0x6c, 0x9f, 0x7b, 0xf7, 0x8f, 0x7e,
+        0xf1, 0xdf, 0xff, 0xf7, 0xe6,
+        0xbf, 0x95, 0x7f, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+        0xfe, 0xbf, 0x5f, 0x80, 0xf7, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0xbc, 0xaf, 0xdf,
+        0xbf, 0x87, 0xfe, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xef, 0x97, 0x89, 0x7f, 0xf8, 0xff, 0xfe,
+        0xef, 0xff, 0xff, 0xef, 0xbb,
+        0xff, 0x3e, 0xdf, 0xff, 0xdf, 0xdf, 0xf9, 0xf7,
+        0xe6, 0x76, 0xf4, 0xdf, 0xff, 0xff, 0xbf, 0x9f,
+        0x9f, 0xef, 0xcf, 0xbc, 0xf1,
+        0xff, 0xfb, 0xdf, 0xf7, 0xda, 0x2f, 0x8e, 0xd5,
+        0xf0, 0xf0, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xce,
+        0x4f, 0xc3, 0x59, 0xb3, 0xff,
+        0xff, 0xff, 0xdf, 0xff, 0xdf, 0xff, 0xfa, 0xff,
+        0xff, 0xdf, 0xf6, 0xdf, 0xbf, 0xfe, 0x9f, 0x9e,
+        0xff, 0xff, 0xef, 0xbf, 0xf7,
+        0xbf, 0x87, 0xd8, 0xf8, 0xda, 0x7f, 0xff, 0xf6,
+        0xff, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xff, 0xff, 0xdb, 0xff, 0xfe, 0xf7,
+        0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbf, 0xef,
+        0xff, 0xff, 0xff, 0xfb, 0xff,
+        0xff, 0x7f, 0xdf, 0xff, 0xfe, 0xff, 0xfb, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xbf, 0xf7, 0x9b, 0xff, 0xde, 0xb7,
+        0xfa, 0xff, 0xff, 0xff, 0xff, 0xff, 0x95, 0xee,
+        0xcd, 0xff, 0xfd, 0xff, 0xff,
+        0xff, 0xff, 0x0f, 0xff, 0xde, 0xff, 0xeb, 0xff,
+        0xfd, 0xf7, 0xff, 0xff, 0xdf, 0xff, 0xfd, 0xff,
+        0xfd, 0xfe, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x2b, 0xfb, 0xa0, 0xad, 0xf7, 0xf5,
+        0xff, 0xff, 0xfe, 0xff, 0x2b, 0xff, 0xf5, 0x27,
+        0x7f, 0xf5, 0xe0, 0xff, 0xee,
+        0xff, 0x67, 0x6f, 0xf3, 0xf9, 0xff, 0x8f, 0xff,
+        0x00, 0xff, 0xd0, 0xff, 0xff, 0xfb, 0xf7, 0xff,
+        0x8f, 0x7f, 0x81, 0x7d, 0xf1,
+        0xff, 0xbf, 0xfd, 0xbf, 0xbf, 0x16, 0x70, 0xf3,
+        0xeb, 0x3f, 0x7f, 0xab, 0xaf, 0xa5, 0xed, 0x4d,
+        0xf1, 0xf7, 0xfd, 0xef, 0xff,
+        0x3f, 0xff, 0xff, 0x9c, 0xf7, 0xdb, 0xfe, 0xfc,
+        0x7f, 0x63, 0x7e, 0xfc, 0x77, 0xda, 0xff, 0x97,
+        0x61, 0xae, 0xeb, 0xf3, 0xb6,
+        0xff, 0xfc, 0xf7, 0xfc, 0x3f, 0x9d, 0xf3, 0xdb,
+        0xff, 0xbb, 0x7d, 0x84, 0x6f, 0xf7, 0xef, 0x1f,
+        0x7e, 0xdb, 0xff, 0xad, 0xfb,
+        0xff, 0xff, 0xaf, 0xff, 0x82, 0xff, 0xe0, 0xff,
+        0xff, 0xfe, 0xff, 0xff, 0xfb, 0x7f, 0xa3, 0x77,
+        0xf1, 0x6d, 0xfa, 0x7f, 0xcb,
+        0xff, 0x9f, 0xf5, 0xaf, 0xef, 0xb5, 0xfb, 0xf6,
+        0xff, 0xff, 0xfd, 0xce, 0xff, 0x75, 0xfb, 0xf7,
+        0x7b, 0x6f, 0xea, 0xff, 0xfb,
+        0xbf, 0xff, 0xd6, 0xef, 0xca, 0xd2, 0xf2, 0xf7,
+        0xff, 0x7f, 0x8d, 0xfb, 0xa1, 0xbf, 0x8d, 0x97,
+        0x71, 0xff, 0xfe, 0xfb, 0xff,
+        0xff, 0xff, 0xc7, 0xdf, 0xf0, 0xff, 0xf2, 0xef,
+        0xd7, 0xef, 0xff, 0xbf, 0x9b, 0x4f, 0xf5, 0xab,
+        0xf7, 0xfb, 0xfe, 0xde, 0xfb,
+        0xff, 0xff, 0xdf, 0xff, 0xef, 0xff, 0xed, 0xef,
+        0xdf, 0xb2, 0xf5, 0xff, 0xdb, 0x7f, 0xbf, 0xff,
+        0xdd, 0xec, 0xfb, 0x76, 0xb3,
+        0xff, 0xdd, 0x0d, 0xaf, 0xd2, 0xf0, 0x7f, 0xff,
+        0xbd, 0xed, 0x7d, 0x7e, 0xaf, 0x8f, 0x71, 0xb1,
+        0x69, 0x73, 0xeb, 0xec, 0x7b,
+        0xbf, 0x7f, 0xa4, 0xff, 0xaa, 0xfc, 0x63, 0xff,
+        0xdf, 0xfd, 0xcf, 0x7f, 0xa8, 0xef, 0xd7, 0x3f,
+        0xd9, 0xd6, 0xfb, 0xf7, 0xd5,
+        0xff, 0xfa, 0xbf, 0xff, 0xae, 0xd7, 0xf8, 0xf7,
+        0xff, 0xff, 0xff, 0xff, 0xfb, 0xff, 0x8d, 0xff,
+        0xf1, 0xbe, 0xbe, 0xfd, 0xef,
+        0x7f, 0xfe, 0xbf, 0xfb, 0xbf, 0xed, 0xb8, 0xd7,
+        0xea, 0xff, 0xff, 0x7f, 0xf7, 0x3f, 0xad, 0x3b,
+        0xb1, 0xef, 0x6f, 0x6e, 0xfa,
+        0xff, 0xff, 0xef, 0xfc, 0xfb, 0xf9, 0xfe, 0xff,
+        0xef, 0xdf, 0xff, 0xff, 0xcf, 0xef, 0xb7, 0xf3,
+        0xaf, 0x7e, 0xfd, 0xfe, 0xf7,
+        0x3f, 0x48, 0xfd, 0xf3, 0xf3, 0xff, 0xcf, 0xbf,
+        0xff, 0x0e, 0x3f, 0xc1, 0xfd, 0xf3, 0xff, 0xff,
+        0xcf, 0x9f, 0xff, 0x8a, 0x6d,
+        0xff, 0xf8, 0x7a, 0xff, 0x77, 0xff, 0xdf, 0xcf,
+        0xef, 0x8f, 0xdd, 0xb1, 0xfb, 0xf7, 0xf7, 0xf7,
+        0xde, 0xbf, 0x4e, 0x0f, 0x3b,
+        0xbf, 0xfc, 0xfc, 0xf7, 0x7f, 0xff, 0xe7, 0xfe,
+        0xff, 0xbf, 0xbd, 0xf0, 0xf6, 0xfb, 0xef, 0xff,
+        0xee, 0xff, 0xff, 0x9d, 0x1f,
+        0xff, 0xf8, 0x7b, 0xff, 0xf7, 0xfe, 0xff, 0xfe,
+        0xbf, 0xbf, 0xf7, 0xf2, 0xeb, 0xff, 0xff, 0xf9,
+        0xff, 0xff, 0x8e, 0x0f, 0x79,
+        0xff, 0xf7, 0xff, 0xfb, 0xf7, 0xff, 0xff, 0xce,
+        0xdf, 0xf7, 0xff, 0xd3, 0xee, 0xf3, 0xf7, 0xff,
+        0xf7, 0x91, 0xef, 0xf1, 0xf7,
+        0xff, 0xfa, 0x7f, 0xf8, 0xf5, 0xff, 0xcf, 0xff,
+        0xf9, 0xf7, 0xf5, 0xdf, 0xff, 0xf1, 0xef, 0xff,
+        0x9f, 0x79, 0xf8, 0xf7, 0xfb,
+        0x7f, 0xd8, 0xff, 0xf7, 0xff, 0xff, 0xf7, 0xbf,
+        0xff, 0xae, 0xdf, 0xf0, 0xeb, 0xf3, 0xef, 0xff,
+        0xff, 0xff, 0xff, 0x87, 0x78,
+        0xbf, 0xfc, 0x7b, 0xfc, 0xf5, 0xff, 0xcf, 0xcf,
+        0xff, 0xf7, 0xa7, 0xf3, 0xec, 0xff, 0xe9, 0xff,
+        0x9f, 0x87, 0xb8, 0xbf, 0xcf,
+        0xff, 0x1d, 0xff, 0xf7, 0xff, 0xcf, 0xff, 0xfe,
+        0xcf, 0xcf, 0xf4, 0xff, 0xfb, 0xfd, 0xff, 0x9f,
+        0xff, 0xf9, 0xae, 0x6f, 0xf8,
+        0xff, 0xf8, 0xff, 0xfe, 0xff, 0x8f, 0xcf, 0xce,
+        0xff, 0xaf, 0xff, 0xf2, 0xfb, 0xf6, 0xff, 0x9f,
+        0x8f, 0x9f, 0xf7, 0xbf, 0x7e,
+        0x3f, 0xd3, 0xff, 0xfb, 0x8f, 0x0f, 0xf0, 0xde,
+        0xff, 0xfd, 0x26, 0xcf, 0x7f, 0xf4, 0x8f, 0x1e,
+        0xf1, 0x99, 0x77, 0xef, 0xb0,
+        0xff, 0x93, 0x7f, 0xf8, 0xff, 0x7f, 0xcf, 0xff,
+        0xff, 0xaf, 0x4d, 0x85, 0xf6, 0xf2, 0xff, 0xff,
+        0x9f, 0xff, 0xfe, 0x9f, 0x3f,
+        0xff, 0x85, 0xff, 0xf4, 0xff, 0xff, 0xcf, 0xff,
+        0x7f, 0xbf, 0xce, 0xab, 0x77, 0xfc, 0xff, 0xfe,
+        0x9f, 0xff, 0xff, 0xff, 0x25,
+        0xff, 0x7f, 0xff, 0xfd, 0xfe, 0xcf, 0xd5, 0xce,
+        0xff, 0x77, 0xf8, 0xff, 0xef, 0xff, 0xef, 0x9f,
+        0x99, 0x8f, 0xe1, 0x6f, 0xf1,
+        0xff, 0xff, 0xff, 0xf7, 0xf6, 0x0f, 0x84, 0x98,
+        0xf0, 0xb0, 0xff, 0xdf, 0xef, 0xff, 0xe7, 0x9e,
+        0x07, 0x8f, 0x61, 0xc3, 0xff,
+        0xff, 0xef, 0xbf, 0xff, 0xbe, 0xff, 0xf2, 0xff,
+        0x7f, 0xcf, 0xf7, 0xb7, 0xff, 0xff, 0xef, 0xfe,
+        0xf7, 0xff, 0xe1, 0xbf, 0xf5,
+        0xbf, 0x87, 0xb8, 0xf8, 0xb6, 0x5f, 0xf6, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xe0, 0xf0, 0xf7, 0x9f,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xef, 0xff, 0xfe, 0xcf, 0xde, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xdf, 0x9f,
+        0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xfe, 0xef, 0xf6, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf7, 0x9e,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x9f, 0xff, 0xbe, 0xff, 0xfa, 0xff,
+        0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xef, 0xfe,
+        0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xbf, 0x7f, 0xbe, 0xff, 0xb6, 0xcf,
+        0xfa, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xf7, 0xff,
+        0xff, 0x8e, 0xff, 0xf1, 0xff,
+        0xff, 0xef, 0x8f, 0xdf, 0xb4, 0x8d, 0xef, 0xe8,
+        0xf5, 0xff, 0xfe, 0xff, 0x0f, 0x3b, 0x71, 0xaf,
+        0x67, 0xf7, 0xea, 0xff, 0xff,
+        0xff, 0x7f, 0xaf, 0xd5, 0xff, 0xf7, 0x0f, 0xff,
+        0x00, 0xbf, 0xf0, 0x7f, 0x5f, 0xbd, 0x75, 0xff,
+        0x8f, 0x7f, 0x81, 0x7f, 0xd1,
+        0xff, 0xbf, 0xef, 0xfe, 0xaa, 0x0c, 0x68, 0xf0,
+        0xff, 0xff, 0x5f, 0xbd, 0xef, 0xef, 0xaf, 0x0b,
+        0x77, 0xb9, 0xff, 0xff, 0xfd,
+        0x3f, 0xe3, 0xee, 0xdb, 0xff, 0xe0, 0xbb, 0xfe,
+        0xdb, 0xf7, 0x3e, 0xef, 0xe5, 0x9b, 0x7b, 0xdd,
+        0x37, 0x3d, 0xcf, 0xf7, 0xbe,
+        0xff, 0xeb, 0xb7, 0xff, 0x2f, 0xbe, 0xfd, 0xb1,
+        0xdf, 0xcf, 0x7b, 0x97, 0x7f, 0xab, 0x7f, 0xff,
+        0x7e, 0xf3, 0xff, 0x9d, 0xbb,
+        0xff, 0xff, 0x07, 0xff, 0x90, 0xec, 0xf0, 0xff,
+        0xfd, 0xf5, 0xff, 0x7f, 0xdf, 0xdf, 0x81, 0x2e,
+        0xf1, 0xff, 0xbf, 0xeb, 0xfa,
+        0xff, 0xb7, 0x57, 0xb8, 0xa7, 0xde, 0xbb, 0xf7,
+        0xff, 0xff, 0xfa, 0xe7, 0xea, 0xb5, 0x7f, 0xf6,
+        0xf5, 0xfb, 0xff, 0xff, 0xbf,
+        0xbf, 0xfe, 0xf3, 0xaf, 0xa9, 0xd6, 0xf4, 0xdf,
+        0xef, 0xff, 0xef, 0xfa, 0xd5, 0xff, 0x99, 0x3f,
+        0x77, 0xff, 0xbf, 0xfb, 0xfe,
+        0xff, 0xff, 0x87, 0xff, 0xb8, 0xfd, 0xfc, 0xf7,
+        0xfb, 0xfe, 0xfe, 0xff, 0xaf, 0x3f, 0x69, 0xe6,
+        0xfb, 0x5f, 0xff, 0xff, 0xdf,
+        0xff, 0xff, 0xfb, 0xfb, 0xcb, 0x7f, 0xbf, 0x9f,
+        0x67, 0xbb, 0xff, 0x77, 0xbf, 0x7f, 0xfd, 0xdf,
+        0xdf, 0xef, 0xfd, 0x5f, 0xff,
+        0xff, 0xf8, 0x1b, 0x9d, 0xd0, 0x70, 0x7b, 0xff,
+        0xbe, 0xfc, 0x7f, 0x78, 0x8f, 0x4d, 0xa9, 0x75,
+        0x3f, 0x7f, 0xff, 0xeb, 0x65,
+        0xbf, 0x7f, 0xb6, 0xdf, 0xb4, 0x76, 0x59, 0xff,
+        0xff, 0xd4, 0xa7, 0x7f, 0xd2, 0xff, 0xe9, 0xdf,
+        0xfd, 0xd7, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xff, 0xfb, 0xbf, 0xff, 0xf4, 0xef,
+        0xdf, 0xb7, 0xf8, 0xdf, 0xdf, 0x7f, 0x8f, 0x7e,
+        0xf1, 0xba, 0xbf, 0x96, 0xef,
+        0x7f, 0xff, 0xef, 0xff, 0x8b, 0xf7, 0xe0, 0xf8,
+        0xef, 0x7f, 0xf2, 0xff, 0xff, 0xff, 0xee, 0xb7,
+        0xf1, 0xf7, 0x5f, 0x7f, 0xff,
+        0xff, 0xff, 0xbf, 0xbf, 0xdc, 0xfe, 0xf5, 0xff,
+        0xfc, 0xf7, 0xff, 0xff, 0xaf, 0xff, 0xe9, 0xf6,
+        0xf9, 0x5f, 0xfb, 0xfb, 0xff,
+        0x3f, 0x78, 0xcc, 0xf3, 0xff, 0xff, 0xdf, 0xdb,
+        0xfb, 0x2f, 0x2b, 0xf1, 0xf5, 0xff, 0xf7, 0xff,
+        0xff, 0xbf, 0xff, 0xc6, 0x4f,
+        0xff, 0xf8, 0x5b, 0xdf, 0x7f, 0xdf, 0xff, 0xaf,
+        0xcb, 0x8e, 0xf5, 0xb5, 0xff, 0xff, 0xff, 0xff,
+        0xfe, 0x9f, 0x4e, 0x4f, 0x79,
+        0xbf, 0xfc, 0xde, 0xf7, 0x77, 0xdf, 0xff, 0xff,
+        0xef, 0x8f, 0xff, 0x99, 0xeb, 0xfd, 0xe5, 0xff,
+        0xfc, 0xf3, 0xdf, 0xdf, 0x7b,
+        0xff, 0xfc, 0x5d, 0xdf, 0xd3, 0xdf, 0xff, 0xff,
+        0xff, 0x9f, 0x9a, 0xf0, 0xe7, 0xff, 0xe9, 0xf1,
+        0xfd, 0xff, 0xe2, 0x6f, 0x7d,
+        0xff, 0xff, 0xcf, 0xfc, 0xf7, 0xff, 0xf7, 0x8f,
+        0xff, 0xef, 0xf9, 0xaf, 0xfd, 0xf8, 0xe3, 0xff,
+        0xfb, 0x89, 0xff, 0xf1, 0xf8,
+        0xff, 0xff, 0x5f, 0xff, 0xd7, 0xdf, 0xa7, 0xff,
+        0xc8, 0xbf, 0xbe, 0x8d, 0xfe, 0xfc, 0xe9, 0xff,
+        0x9b, 0x61, 0xfe, 0xf3, 0xff,
+        0x7f, 0xd8, 0xdf, 0xf7, 0xd7, 0xff, 0xaf, 0xff,
+        0xff, 0x8f, 0xff, 0x84, 0xef, 0xf6, 0xe9, 0xff,
+        0xd9, 0x8d, 0xff, 0xb7, 0x78,
+        0xbf, 0xfc, 0x5b, 0xfc, 0xf5, 0xdf, 0xdf, 0x8f,
+        0xaf, 0x87, 0xf7, 0xd2, 0xed, 0xff, 0xef, 0xff,
+        0xb1, 0x85, 0xbc, 0xbd, 0xff,
+        0xff, 0xbe, 0x7f, 0xf5, 0xff, 0x9f, 0xff, 0xfb,
+        0x8f, 0xff, 0xf4, 0xef, 0xfa, 0xf5, 0xff, 0xbf,
+        0xff, 0xfb, 0x9e, 0x5f, 0xf0,
+        0xff, 0x58, 0xfa, 0xfb, 0xff, 0x9f, 0x9f, 0x8f,
+        0xf7, 0xaf, 0xff, 0x93, 0xfb, 0xfe, 0xff, 0xbf,
+        0xaf, 0xbf, 0xf1, 0xcf, 0x5f,
+        0x3f, 0xc3, 0xfd, 0xf9, 0x8f, 0x1f, 0xb0, 0xbf,
+        0xbf, 0xeb, 0x6f, 0xef, 0x77, 0xf5, 0x8f, 0x3e,
+        0xf1, 0x99, 0x63, 0xaf, 0xfe,
+        0xff, 0xb0, 0x7f, 0xfc, 0xff, 0x7f, 0x8f, 0xff,
+        0xff, 0x9f, 0x7f, 0xfc, 0xf5, 0xf1, 0xff, 0xff,
+        0xbf, 0xff, 0xde, 0x9f, 0x7b,
+        0xff, 0x86, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xff, 0xff, 0xeb, 0x75, 0xf5, 0xff, 0xfe,
+        0xaf, 0xff, 0xff, 0xff, 0x6b,
+        0xff, 0x7f, 0xcf, 0xf7, 0xc7, 0x9f, 0xb3, 0x8b,
+        0xeb, 0x77, 0xfe, 0xef, 0xff, 0xff, 0x9f, 0xbf,
+        0xb1, 0x8f, 0xe3, 0x6f, 0xf1,
+        0xff, 0xff, 0xef, 0xfb, 0xfd, 0x1f, 0x85, 0x9e,
+        0xd0, 0x90, 0xf7, 0xbb, 0xff, 0xfe, 0xdf, 0xae,
+        0x0f, 0xed, 0x71, 0xfb, 0xfd,
+        0xff, 0xff, 0xcf, 0xff, 0xe7, 0xbf, 0xf5, 0xfb,
+        0xff, 0xff, 0xf9, 0xfd, 0xff, 0xff, 0xdf, 0xfe,
+        0xfb, 0xff, 0xf3, 0xbf, 0xfd,
+        0xbf, 0x86, 0xe8, 0xf0, 0xff, 0x7f, 0xf5, 0xff,
+        0xff, 0xef, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xbf,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xfe, 0xff, 0xfe, 0xef, 0xaf, 0xf5, 0xff,
+        0x7f, 0xff, 0xff, 0xef, 0xef, 0xff, 0xef, 0xaf,
+        0xfd, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xcf, 0xf7, 0xcf, 0xff, 0xfd, 0xff,
+        0xff, 0xef, 0xff, 0xff, 0xef, 0xff, 0xff, 0xee,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xef, 0xaf, 0xf5, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xcf, 0xbe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xfe, 0xcf, 0xff, 0xef, 0xff, 0xfd, 0x8f,
+        0xfa, 0xe5, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
+        0xff, 0x8e, 0xff, 0xf1, 0xff,
+        0xff, 0xff, 0x0e, 0xdf, 0xfa, 0x8f, 0xb3, 0xf0,
+        0xdf, 0xff, 0xfa, 0xff, 0x0f, 0x7b, 0x71, 0x87,
+        0x5f, 0xf1, 0xfe, 0xf7, 0xfe,
+        0xff, 0x1f, 0x7f, 0x83, 0xff, 0xef, 0x0f, 0xff,
+        0x00, 0xef, 0xe0, 0xdd, 0x5f, 0xb7, 0x7f, 0xf1,
+        0x8f, 0x7d, 0x81, 0x67, 0xe1,
+        0xff, 0xf9, 0xaf, 0xfd, 0x9c, 0x5a, 0x7a, 0xfa,
+        0xf7, 0xff, 0x7f, 0xff, 0x8f, 0xea, 0xb9, 0x6f,
+        0x61, 0xf1, 0xf3, 0xff, 0xff,
+        0x3f, 0xe7, 0xf9, 0xdf, 0xba, 0x6f, 0xff, 0xff,
+        0x4e, 0xfe, 0x1e, 0xee, 0xfd, 0xef, 0x73, 0xed,
+        0xfd, 0x5b, 0x7d, 0xf7, 0xfe,
+        0xff, 0x62, 0xf7, 0xdd, 0xff, 0xbe, 0xfb, 0xfd,
+        0xff, 0x95, 0x7b, 0xbe, 0x7e, 0xb5, 0x7f, 0xd3,
+        0x7e, 0xfb, 0xef, 0x1d, 0x7f,
+        0xff, 0x7f, 0xcf, 0xff, 0xeb, 0xdf, 0xe2, 0xbe,
+        0x7b, 0xeb, 0xff, 0x73, 0x0f, 0x9f, 0x85, 0x76,
+        0x75, 0xdf, 0xf6, 0x6b, 0xfb,
+        0xff, 0x1f, 0xe1, 0xfa, 0xdf, 0xeb, 0xdf, 0xfb,
+        0xdf, 0xff, 0xfe, 0xef, 0xdc, 0xa3, 0x7d, 0xe6,
+        0xfd, 0xef, 0xfe, 0xf7, 0xd5,
+        0xbf, 0x7f, 0xf6, 0xff, 0xa6, 0xbe, 0xf2, 0xbf,
+        0x7f, 0xfd, 0xc3, 0xff, 0xf7, 0xff, 0x8f, 0x5f,
+        0xf5, 0xf7, 0xef, 0xff, 0xaf,
+        0xff, 0xff, 0x87, 0xbf, 0xf2, 0xe7, 0xee, 0xda,
+        0xf7, 0xff, 0xf7, 0xff, 0xaf, 0x6b, 0x69, 0xf4,
+        0xff, 0xbf, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x6f, 0xfb, 0x97, 0xef, 0xfb, 0xfb,
+        0x3d, 0xff, 0xbe, 0xfb, 0xf7, 0x7e, 0xb9, 0x9f,
+        0xff, 0xcf, 0xaf, 0x57, 0xff,
+        0xff, 0xd8, 0x18, 0x8e, 0xf2, 0xf2, 0xdf, 0xff,
+        0x9e, 0xef, 0x6f, 0x7e, 0xbf, 0x0b, 0xf5, 0x73,
+        0x7d, 0x7f, 0x5f, 0xef, 0xb3,
+        0xbf, 0x7f, 0xd5, 0x97, 0xf2, 0xea, 0x7f, 0xf7,
+        0xfe, 0xd5, 0x87, 0x5f, 0xbf, 0x8f, 0xf7, 0xff,
+        0xff, 0xf3, 0xff, 0xb7, 0xcf,
+        0xff, 0xff, 0xff, 0x3f, 0x93, 0xff, 0xf0, 0xaf,
+        0xfe, 0x35, 0xf9, 0xff, 0xbf, 0x7b, 0x8f, 0x7e,
+        0xb5, 0xff, 0xff, 0xfb, 0xef,
+        0x7f, 0xff, 0x7f, 0x7f, 0x8f, 0xef, 0xfa, 0xd9,
+        0xff, 0x7a, 0xf8, 0xff, 0xa5, 0xc6, 0x8a, 0xe7,
+        0xf3, 0xcf, 0x5f, 0xbf, 0xec,
+        0xff, 0xff, 0x9f, 0xcf, 0xbc, 0xfa, 0xbf, 0xff,
+        0xfe, 0x7f, 0xff, 0xff, 0xff, 0xdf, 0xfd, 0xf6,
+        0xef, 0xff, 0xff, 0xff, 0xfd,
+        0xff, 0xff, 0xff, 0xaf, 0xff, 0xff, 0xdf, 0xae,
+        0xff, 0xf7, 0xff, 0xff, 0xff, 0xcf, 0xfb, 0xf7,
+        0xff, 0xdb, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x7f, 0x7f, 0x9f, 0xcf, 0xf0,
+        0x71, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xf9, 0xcf,
+        0x2f, 0x71, 0xf4, 0xff, 0xff,
+        0x3f, 0x7a, 0xfa, 0xf7, 0xff, 0xff, 0xef, 0xaf,
+        0xf5, 0x0b, 0x01, 0xf1, 0xbf, 0xff, 0xff, 0xff,
+        0xcf, 0xbf, 0xaf, 0x8a, 0x5e,
+        0xff, 0xf8, 0x7f, 0xfd, 0x7d, 0xff, 0xef, 0xef,
+        0xbd, 0x9e, 0xdf, 0xfd, 0xbf, 0xbd, 0xbd, 0xfd,
+        0xcc, 0xbf, 0x4e, 0x0d, 0x35,
+        0xff, 0xfe, 0xfe, 0xf7, 0x5f, 0xdf, 0xff, 0xf7,
+        0xb7, 0x8f, 0xc7, 0xf1, 0xbf, 0xf9, 0xbf, 0xff,
+        0xfc, 0xf7, 0xef, 0x0f, 0x1f,
+        0xff, 0xf8, 0x5d, 0xff, 0xff, 0xdf, 0xff, 0xff,
+        0xc7, 0x8f, 0xff, 0xf9, 0xbf, 0xff, 0xbd, 0xf5,
+        0xfd, 0xff, 0xc6, 0x8f, 0x75,
+        0xbf, 0xfa, 0xdf, 0xba, 0xdd, 0xff, 0xfd, 0xad,
+        0xff, 0xdd, 0xb7, 0xdb, 0xf9, 0xf3, 0xff, 0xdf,
+        0xf9, 0xcd, 0xff, 0xfd, 0xbf,
+        0xff, 0xef, 0x5f, 0xfa, 0xdf, 0xff, 0xed, 0xbf,
+        0xfa, 0xfd, 0xfb, 0xdf, 0xff, 0xf3, 0xff, 0xff,
+        0xa9, 0x77, 0xf2, 0xfd, 0xff,
+        0x7f, 0xf8, 0x9a, 0xf7, 0xdf, 0xff, 0xe7, 0xff,
+        0xff, 0x8b, 0xdf, 0xdc, 0xf7, 0xfd, 0xff, 0xff,
+        0xe5, 0xbf, 0xff, 0x89, 0x5c,
+        0xbf, 0xfe, 0x99, 0xfe, 0xdb, 0xff, 0xf7, 0xed,
+        0xef, 0xc5, 0xaf, 0xf1, 0xde, 0xff, 0xf7, 0xdf,
+        0xdd, 0xc7, 0xfe, 0xfd, 0x8f,
+        0xff, 0x96, 0xff, 0xf5, 0xff, 0xff, 0xff, 0x9f,
+        0xaf, 0xf7, 0xd0, 0xa7, 0xf1, 0xfc, 0xff, 0xff,
+        0xff, 0xdd, 0xae, 0x7f, 0xf9,
+        0xff, 0xf8, 0xfa, 0xff, 0xff, 0xff, 0xdf, 0xff,
+        0xf5, 0x8d, 0xdf, 0xf4, 0xf7, 0xfb, 0xff, 0xff,
+        0xdf, 0xfd, 0xf7, 0x8e, 0x7f,
+        0x3f, 0xf7, 0xfd, 0xf9, 0x8f, 0x7f, 0xf0, 0xff,
+        0xbd, 0xbf, 0x6f, 0x9f, 0x7c, 0xf3, 0x8f, 0x7e,
+        0xf1, 0xfd, 0x57, 0xfb, 0xae,
+        0xff, 0x88, 0x7d, 0xfc, 0xff, 0x7f, 0xff, 0xff,
+        0xfd, 0xbf, 0x57, 0xac, 0xfb, 0xf8, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0xdf, 0x67,
+        0xff, 0x86, 0xfd, 0xf8, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xaf, 0xfe, 0xad, 0x7b, 0xfe, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xdf, 0x3f,
+        0xff, 0x7f, 0xdf, 0xf7, 0xbf, 0xff, 0xfb, 0xff,
+        0x8d, 0x35, 0xfc, 0xf6, 0xff, 0xff, 0xbd, 0xff,
+        0xd3, 0xdd, 0xa5, 0x7f, 0xf5,
+        0xff, 0xff, 0xff, 0xff, 0x9d, 0x2f, 0xcd, 0x8a,
+        0xd0, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xbd, 0xae,
+        0x4d, 0x09, 0x51, 0xeb, 0xff,
+        0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xfd, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0xfd, 0xbd, 0xfe,
+        0xf9, 0xf7, 0xff, 0xff, 0xf6,
+        0xbf, 0x87, 0xf8, 0xf0, 0xfd, 0x7f, 0xff, 0xfd,
+        0xdf, 0xdf, 0x87, 0x8f, 0xf0, 0xf0, 0x9d, 0xdf,
+        0xfd, 0xfd, 0xcf, 0xdf, 0x8f,
+        0xff, 0xff, 0xdf, 0xff, 0xf7, 0xef, 0xed, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbd, 0xff,
+        0xfd, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xe7, 0xff, 0xf7, 0xdd, 0xff, 0xff, 0xef,
+        0xdb, 0xff, 0xff, 0xdf, 0xff, 0xf7, 0xbd, 0xfe,
+        0xfd, 0xef, 0xdb, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xfd, 0xff,
+        0xff, 0xdf, 0xd7, 0xff, 0x77, 0xff, 0xbd, 0xfe,
+        0xfd, 0xff, 0xef, 0xdf, 0xcf,
+        0xff, 0xe7, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xdf,
+        0xde, 0xf5, 0xdf, 0xd7, 0xf7, 0xf7, 0xbd, 0xff,
+        0xfd, 0x5e, 0xdf, 0xf5, 0xcf,
+        0xff, 0xef, 0x9f, 0x7a, 0xf0, 0xf7, 0xff, 0xf0,
+        0xf7, 0xff, 0xbe, 0xff, 0xaf, 0x6f, 0xf1, 0x8f,
+        0x7d, 0xf9, 0xfe, 0xff, 0xff,
+        0xbf, 0x7f, 0xfb, 0xb6, 0xff, 0xf5, 0x8f, 0xff,
+        0x00, 0xbf, 0xd0, 0x6f, 0xaf, 0xfe, 0x77, 0xfd,
+        0x8f, 0x7f, 0x81, 0x5d, 0xe1,
+        0xff, 0x9b, 0x7f, 0xd9, 0xc8, 0x0a, 0x74, 0xfc,
+        0xf5, 0x7f, 0x7f, 0xff, 0x9f, 0x7b, 0xcb, 0xeb,
+        0x75, 0xf1, 0xf7, 0xff, 0xff,
+        0x7f, 0xe7, 0x6d, 0x9f, 0xfe, 0xff, 0xa5, 0xe9,
+        0x7e, 0x7a, 0xa8, 0xdf, 0xf3, 0xfd, 0x73, 0xad,
+        0xbd, 0xdb, 0xff, 0xff, 0xfe,
+        0xff, 0xd2, 0x77, 0xff, 0x4d, 0x8e, 0xff, 0x9f,
+        0xff, 0xdf, 0x6e, 0xf8, 0x67, 0xf1, 0xcf, 0x97,
+        0x3e, 0xf7, 0xe7, 0xfe, 0xbf,
+        0xff, 0xff, 0x8d, 0xff, 0x8f, 0xdf, 0xf2, 0xee,
+        0xf7, 0x65, 0xfe, 0xef, 0x2f, 0xaf, 0xe7, 0xff,
+        0xf3, 0xff, 0x7f, 0xbf, 0xfe,
+        0xff, 0xbf, 0x67, 0xf4, 0xef, 0x9f, 0xff, 0xff,
+        0x7f, 0x5f, 0x8e, 0xff, 0xf8, 0xef, 0xf7, 0xff,
+        0xff, 0x77, 0xff, 0xee, 0xb5,
+        0xbf, 0xff, 0x12, 0xff, 0xc2, 0xde, 0xf2, 0xf7,
+        0x2f, 0xbe, 0xff, 0xff, 0xff, 0xff, 0x6b, 0x7b,
+        0x71, 0xff, 0xcf, 0xff, 0xde,
+        0xff, 0x7b, 0x03, 0xdf, 0xb2, 0xf7, 0xf6, 0xfe,
+        0xff, 0xff, 0xdb, 0xff, 0xcf, 0x6f, 0xd7, 0xaf,
+        0xff, 0xfb, 0xfd, 0x77, 0xff,
+        0xff, 0x7f, 0xcf, 0x7f, 0xff, 0xef, 0xeb, 0x9b,
+        0x65, 0xf7, 0xf6, 0x7f, 0xe7, 0x7d, 0xf7, 0xff,
+        0xff, 0xc5, 0xfb, 0x59, 0xfb,
+        0xff, 0x3a, 0x1f, 0x2f, 0xdc, 0xf4, 0xef, 0xee,
+        0xce, 0xae, 0x6f, 0x3c, 0x0d, 0x0f, 0x61, 0x35,
+        0xdf, 0x7f, 0xbb, 0xbf, 0x77,
+        0xff, 0xff, 0xb2, 0xbf, 0x7e, 0xe6, 0xfd, 0xff,
+        0x7a, 0xdd, 0xe7, 0xff, 0xda, 0xaf, 0x71, 0xdf,
+        0xef, 0xb4, 0xef, 0xeb, 0x8b,
+        0xff, 0xff, 0xdb, 0xff, 0x9f, 0xfd, 0xf2, 0xfd,
+        0xdf, 0x7d, 0xfb, 0xfb, 0xff, 0xb7, 0xeb, 0x7f,
+        0xf3, 0xfa, 0xbf, 0xfe, 0xdf,
+        0x7f, 0x7f, 0xff, 0xff, 0xaf, 0xfb, 0xf8, 0xe3,
+        0xef, 0x7a, 0xfa, 0x7f, 0xfb, 0xef, 0x7f, 0xbf,
+        0xd3, 0xed, 0x7e, 0xf7, 0xff,
+        0xff, 0xf7, 0x3f, 0xaf, 0xf6, 0xf8, 0xff, 0xff,
+        0xfe, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xf7, 0xf3,
+        0xaf, 0xff, 0xfb, 0xfe, 0xff,
+        0x3f, 0x78, 0xc8, 0xf7, 0xfb, 0xff, 0xff, 0xff,
+        0xfd, 0x0b, 0x2f, 0xd1, 0xb9, 0xf7, 0xff, 0xff,
+        0xcf, 0xbe, 0xf7, 0x86, 0x0f,
+        0xbf, 0xf8, 0x7f, 0xef, 0x5b, 0xff, 0xff, 0xbd,
+        0xcf, 0x86, 0xf9, 0xb1, 0x9f, 0x97, 0x9b, 0xe3,
+        0xff, 0xff, 0x46, 0xcd, 0x71,
+        0xff, 0xb8, 0xcc, 0xf7, 0x6b, 0xbf, 0xf9, 0xdf,
+        0xff, 0xeb, 0xff, 0xe1, 0xb5, 0xfb, 0x9b, 0xef,
+        0xdb, 0xe7, 0xff, 0x8f, 0x07,
+        0xff, 0xf8, 0x7d, 0xff, 0xdb, 0xff, 0xb9, 0xff,
+        0xbf, 0x9f, 0xfd, 0xf1, 0x97, 0xef, 0x97, 0xf6,
+        0xe7, 0xf7, 0x8e, 0x8f, 0xfc,
+        0xff, 0xe7, 0xcb, 0xfd, 0xeb, 0xbf, 0xf9, 0xef,
+        0xff, 0x8d, 0xdf, 0x8b, 0xbb, 0xf3, 0x97, 0xef,
+        0xfb, 0xe7, 0xdf, 0xeb, 0xfa,
+        0xff, 0xfd, 0x7f, 0xf9, 0xdb, 0xff, 0x9d, 0xef,
+        0xb2, 0xfd, 0xf3, 0x8f, 0xb7, 0xf3, 0x9b, 0xff,
+        0x8f, 0x7f, 0xfc, 0xfb, 0xfe,
+        0x7f, 0xf8, 0x8b, 0xff, 0xeb, 0xff, 0xfb, 0x8f,
+        0xff, 0x8b, 0xcf, 0xc4, 0xff, 0xf7, 0x82, 0xfe,
+        0xf3, 0x9f, 0xff, 0x93, 0x7e,
+        0xbf, 0xfb, 0x78, 0xb7, 0xdb, 0xff, 0xff, 0xcf,
+        0xef, 0x85, 0xb7, 0xb3, 0xdc, 0xff, 0x96, 0xff,
+        0xe7, 0xcf, 0xee, 0xef, 0x96,
+        0xff, 0xbf, 0x7f, 0xb8, 0xff, 0xff, 0xff, 0xff,
+        0xcf, 0xff, 0xd0, 0xcf, 0xfb, 0xb8, 0xff, 0xbf,
+        0xff, 0xff, 0xde, 0x5f, 0xf1,
+        0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0x9f, 0xff,
+        0xff, 0xcd, 0xff, 0xfc, 0xff, 0xf7, 0xff, 0xef,
+        0xbf, 0xff, 0xf7, 0xae, 0x6f,
+        0x3f, 0xf7, 0xfc, 0xf3, 0x8f, 0x7f, 0xb0, 0xff,
+        0xff, 0xfe, 0x4f, 0x9f, 0x7c, 0xfb, 0x8f, 0x6e,
+        0xb1, 0xff, 0xbf, 0xfd, 0xfe,
+        0xff, 0x88, 0x7b, 0xfa, 0xff, 0x7f, 0xff, 0xbf,
+        0xbd, 0xdf, 0x5f, 0x8c, 0xfb, 0xf1, 0xff, 0xff,
+        0xff, 0xbf, 0xee, 0xcf, 0xff,
+        0xff, 0x86, 0xfb, 0xf0, 0xff, 0xff, 0xdf, 0xff,
+        0x4f, 0xbf, 0xff, 0x85, 0x7b, 0xf8, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0x9f, 0x7f,
+        0xff, 0xbf, 0xff, 0xff, 0xfb, 0xff, 0xbf, 0xef,
+        0xef, 0x79, 0xf4, 0xb7, 0xff, 0xff, 0x83, 0xaf,
+        0xa7, 0xff, 0xb7, 0x77, 0xf9,
+        0xff, 0xfd, 0xff, 0xf7, 0xf7, 0x1f, 0x83, 0xae,
+        0xf0, 0xf4, 0xff, 0xf3, 0xdf, 0xff, 0xf7, 0xae,
+        0x0b, 0x95, 0x73, 0xd1, 0xf7,
+        0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xbb, 0xff,
+        0xff, 0xbf, 0xff, 0xfb, 0xdf, 0xfe, 0xdb, 0xfe,
+        0xe7, 0xff, 0xc7, 0xff, 0xf9,
+        0x3f, 0x87, 0xf8, 0xf8, 0xf3, 0x7f, 0xf7, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xd7, 0xbf,
+        0xfb, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0x8f, 0xff, 0x8d, 0xff, 0xf7, 0xbf,
+        0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xd7, 0xff,
+        0xf3, 0xbf, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0xf7, 0x8b, 0xff, 0xf1, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xf3, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xff, 0xcf, 0xff, 0xcd, 0xff, 0xf7, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xf3, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xcf, 0x7f, 0xcb, 0xff, 0xf1, 0xcf,
+        0xfe, 0xf1, 0xff, 0xff, 0xff, 0xff, 0xf3, 0xff,
+        0xff, 0xce, 0xff, 0xf3, 0xff,
+        0xff, 0xff, 0x8d, 0xfb, 0xbb, 0xaa, 0xff, 0xf8,
+        0xff, 0xf7, 0xff, 0xff, 0x4f, 0x0f, 0x71, 0x89,
+        0x7f, 0xf8, 0xde, 0xff, 0xfa,
+        0xbf, 0xfb, 0x6f, 0xb6, 0xff, 0xfb, 0x0f, 0xff,
+        0x00, 0xbf, 0xc0, 0x7f, 0xef, 0xd3, 0x7b, 0xfd,
+        0x8f, 0x7f, 0x81, 0x7f, 0xe1,
+        0xff, 0xdd, 0xef, 0xdd, 0x9d, 0x0f, 0x56, 0xf8,
+        0xdf, 0xdf, 0x7f, 0xbf, 0xff, 0xff, 0x8f, 0x57,
+        0x71, 0xf1, 0xff, 0xff, 0xff,
+        0x7f, 0xf7, 0xf8, 0xcf, 0xff, 0xb9, 0xd7, 0xfb,
+        0xff, 0xff, 0xff, 0x5e, 0xd1, 0xff, 0x6b, 0xd5,
+        0xff, 0x7b, 0xd5, 0xfd, 0x9a,
+        0xff, 0xfc, 0xb7, 0xbf, 0xde, 0x2f, 0xfe, 0xf4,
+        0xef, 0xc5, 0x7f, 0xa4, 0xff, 0xdd, 0x3f, 0xe1,
+        0x7e, 0xf5, 0xe7, 0xc7, 0xfd,
+        0xff, 0xff, 0xab, 0xa7, 0x9e, 0xde, 0xf8, 0xff,
+        0xff, 0xfe, 0xff, 0xfb, 0x0f, 0xeb, 0xe3, 0x7b,
+        0x71, 0xe5, 0xff, 0x3f, 0xfd,
+        0xff, 0x8f, 0xb7, 0xfc, 0xfc, 0xfb, 0xff, 0xff,
+        0xff, 0xff, 0xbd, 0xdf, 0x7e, 0xeb, 0x3f, 0xd9,
+        0xf7, 0xff, 0xbc, 0x6f, 0xff,
+        0xbf, 0xff, 0xd6, 0xff, 0xaf, 0xf9, 0xd0, 0xfe,
+        0xef, 0xfe, 0xc7, 0xff, 0xfd, 0xcf, 0x87, 0x5b,
+        0xf9, 0xfd, 0xef, 0xff, 0x29,
+        0xff, 0xf7, 0xa7, 0xbf, 0xe0, 0xee, 0xf9, 0x97,
+        0xff, 0xf9, 0xfe, 0xff, 0xcf, 0x3f, 0x59, 0xfd,
+        0xeb, 0xb7, 0xff, 0xfb, 0xff,
+        0xff, 0xfb, 0xbf, 0xff, 0xf6, 0x6f, 0xff, 0xd7,
+        0xff, 0xf5, 0xb6, 0xff, 0xf7, 0x7f, 0xed, 0xff,
+        0xff, 0xff, 0xb7, 0x77, 0xf1,
+        0xff, 0xfc, 0xaf, 0xcf, 0xb8, 0x75, 0x7a, 0xff,
+        0xbf, 0xff, 0xfc, 0xf0, 0xf7, 0x0f, 0xf5, 0x09,
+        0x67, 0x7d, 0xf5, 0x9d, 0xfd,
+        0xbf, 0xff, 0xe0, 0xef, 0xdd, 0x7d, 0x77, 0xff,
+        0xff, 0xdb, 0x8f, 0x7f, 0xf8, 0xff, 0x8f, 0xfb,
+        0xfd, 0x4e, 0xf7, 0xf7, 0x87,
+        0xff, 0xfb, 0xbf, 0xff, 0x8e, 0xff, 0xf8, 0xff,
+        0xbf, 0xbe, 0x7b, 0xff, 0xfe, 0x7f, 0x8d, 0x7d,
+        0xf5, 0xfe, 0xf7, 0xfe, 0xfb,
+        0x7f, 0xff, 0xff, 0xff, 0xef, 0xef, 0xa5, 0xcf,
+        0xff, 0xff, 0xd7, 0x7f, 0xff, 0xaf, 0x8f, 0xcf,
+        0xf9, 0xff, 0x5f, 0x79, 0xfc,
+        0xff, 0xff, 0xcf, 0xef, 0xf9, 0x75, 0xaf, 0xff,
+        0xff, 0xff, 0xff, 0xbf, 0xdf, 0x9f, 0xe7, 0xfd,
+        0xfb, 0x7f, 0xf7, 0x6e, 0xfb,
+        0x3f, 0x58, 0xf9, 0xf7, 0xff, 0xff, 0xdf, 0xaf,
+        0xf2, 0x19, 0x5f, 0xb5, 0xf5, 0xff, 0xfd, 0xff,
+        0xcf, 0xbf, 0xf3, 0x9a, 0x5c,
+        0xbf, 0xd1, 0x7f, 0xff, 0x7f, 0xde, 0xff, 0xf3,
+        0xdf, 0x95, 0xf1, 0xb1, 0xff, 0xff, 0xf3, 0xcb,
+        0xf8, 0xc3, 0x7e, 0x8b, 0x53,
+        0xbf, 0xf8, 0xf9, 0xf6, 0x7f, 0xff, 0xff, 0xff,
+        0xbe, 0x8f, 0xc3, 0xf1, 0xff, 0xfd, 0xfd, 0xff,
+        0xf0, 0xbb, 0xdf, 0x8d, 0x2f,
+        0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xfe, 0xff,
+        0x8f, 0x8f, 0xfb, 0xf1, 0xff, 0xff, 0xff, 0xf9,
+        0xf9, 0xfb, 0xae, 0x0f, 0x73,
+        0xff, 0xff, 0xfe, 0xfd, 0xff, 0xef, 0xfe, 0xdf,
+        0xff, 0xf6, 0xfe, 0xef, 0xf5, 0xfe, 0xfd, 0xff,
+        0xfb, 0xc9, 0xff, 0xf3, 0xdb,
+        0xff, 0xf9, 0x7f, 0xf8, 0xff, 0xff, 0x8f, 0xff,
+        0xf1, 0xfe, 0xef, 0xee, 0xff, 0xfe, 0xfb, 0xff,
+        0x89, 0x7f, 0xf6, 0xfb, 0xff,
+        0x7f, 0xe8, 0xfe, 0xf7, 0xff, 0xff, 0xff, 0xbf,
+        0xff, 0xab, 0xef, 0xf8, 0xbf, 0xff, 0xbc, 0xfe,
+        0xd9, 0xbf, 0xf7, 0x8f, 0x7c,
+        0xbf, 0xfa, 0x79, 0xfa, 0xef, 0xff, 0xde, 0xdf,
+        0xf7, 0xd6, 0xaf, 0xd7, 0xb8, 0xf7, 0xbe, 0xff,
+        0xe9, 0xcf, 0xee, 0xc3, 0xaf,
+        0xff, 0x07, 0xff, 0xf3, 0xff, 0xcf, 0xff, 0xf7,
+        0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xcf,
+        0xff, 0xf9, 0x8e, 0x7f, 0xd1,
+        0xff, 0xf9, 0xff, 0xfc, 0xff, 0xcf, 0xcf, 0xf7,
+        0xf7, 0x8e, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xcf,
+        0xcf, 0xf9, 0xfd, 0x8f, 0x7f,
+        0x3f, 0xef, 0xff, 0xfe, 0x8f, 0x4f, 0xe0, 0xd7,
+        0xef, 0xf9, 0x1f, 0xb3, 0x70, 0xf3, 0x8f, 0x4e,
+        0xd1, 0xf9, 0x7f, 0xdf, 0x82,
+        0xff, 0x82, 0x7e, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xbe, 0xcf, 0x7f, 0x84, 0xff, 0xfa, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0xdf, 0x7f,
+        0xff, 0x81, 0xfe, 0xf0, 0xff, 0xff, 0xdf, 0xff,
+        0x77, 0xcf, 0xbe, 0x8b, 0x7f, 0xf0, 0xff, 0xfe,
+        0xef, 0xff, 0xff, 0xaf, 0x5f,
+        0xff, 0xfa, 0xff, 0xff, 0xeb, 0xdf, 0xcf, 0xd7,
+        0x87, 0x32, 0xf2, 0xbf, 0xff, 0xfb, 0xb9, 0xcf,
+        0xcf, 0xc9, 0xaf, 0x5d, 0xfb,
+        0xff, 0xfb, 0xef, 0xf7, 0xfb, 0x0f, 0x8f, 0xa5,
+        0xf0, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xf9, 0x8e,
+        0x01, 0xc1, 0x71, 0xf3, 0xfd,
+        0x7f, 0xfe, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff,
+        0x6f, 0xff, 0xfa, 0xfd, 0xff, 0xf5, 0xb9, 0xfe,
+        0xc9, 0xff, 0xff, 0xff, 0xfb,
+        0xbf, 0x9f, 0xf8, 0xf8, 0xfb, 0x4f, 0xff, 0xf7,
+        0xdf, 0xdf, 0x87, 0xa7, 0xf0, 0xf8, 0xf9, 0xff,
+        0xf9, 0xff, 0xcf, 0xcf, 0x8e,
+        0xff, 0xff, 0xff, 0xff, 0xfa, 0xdf, 0xdf, 0xf7,
+        0x77, 0xff, 0xdf, 0xff, 0xf7, 0xff, 0xb9, 0xdf,
+        0xf9, 0xf7, 0xf7, 0xff, 0xcf,
+        0xff, 0xe7, 0xff, 0xf7, 0xfb, 0xff, 0xfe, 0xff,
+        0xdf, 0xff, 0xf7, 0xdf, 0xff, 0xf7, 0xf9, 0xfe,
+        0xb1, 0xff, 0xcf, 0xff, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xfa, 0xff, 0xff, 0xff,
+        0xff, 0xdd, 0xdf, 0xf7, 0xf7, 0xff, 0xb1, 0xde,
+        0xf9, 0xff, 0xff, 0xcf, 0xcf,
+        0xff, 0xff, 0xff, 0x7f, 0xfb, 0xbf, 0xbe, 0xcf,
+        0xdf, 0xf2, 0xf7, 0xff, 0xff, 0xff, 0xf1, 0xbf,
+        0xf9, 0xce, 0xcf, 0xf1, 0xff,
+        0xff, 0xff, 0x9f, 0xaf, 0xf4, 0xa7, 0xff, 0xf7,
+        0xff, 0xff, 0xfe, 0xff, 0x0f, 0x6f, 0x79, 0x8f,
+        0x39, 0xf9, 0xde, 0xff, 0xf7,
+        0xff, 0x97, 0xbf, 0xf6, 0xf6, 0xff, 0x0f, 0xdf,
+        0x00, 0xef, 0xf0, 0x67, 0x75, 0xae, 0x7f, 0xfb,
+        0x8f, 0x3f, 0x80, 0x5f, 0xd1,
+        0xff, 0xfd, 0xff, 0xdf, 0x8f, 0x5d, 0x70, 0xfc,
+        0xff, 0xdf, 0x7f, 0xdd, 0x9f, 0xd7, 0xcf, 0x0d,
+        0x75, 0xb1, 0xff, 0xff, 0xfd,
+        0x7f, 0xff, 0xfb, 0xdc, 0xfe, 0xbd, 0xdb, 0xd6,
+        0x7d, 0xf9, 0xae, 0xff, 0xdf, 0xa9, 0x73, 0xdd,
+        0xed, 0x6e, 0x5f, 0xff, 0xf6,
+        0xff, 0xe2, 0xf7, 0xbe, 0xcf, 0xe6, 0xfd, 0xf9,
+        0xff, 0xff, 0x7e, 0xce, 0xff, 0xed, 0x5f, 0xe7,
+        0x7e, 0xbb, 0xef, 0x6b, 0x7f,
+        0xff, 0xff, 0x07, 0xbf, 0x80, 0xd7, 0xf0, 0xfd,
+        0xf7, 0xf3, 0xfb, 0xff, 0x7f, 0xff, 0xc5, 0x6e,
+        0x71, 0xdf, 0xff, 0x7f, 0xfe,
+        0xff, 0xbf, 0x77, 0xb9, 0xfb, 0xc7, 0xfa, 0xfd,
+        0xaf, 0xff, 0xc7, 0xbf, 0x7c, 0xe3, 0x7f, 0xfa,
+        0xff, 0x75, 0xbf, 0xff, 0x87,
+        0xbf, 0xff, 0xc4, 0xff, 0xbc, 0xff, 0xf2, 0xfe,
+        0xdb, 0xb7, 0xff, 0x7f, 0xd3, 0xff, 0xa5, 0x73,
+        0xf1, 0xff, 0xfe, 0xfe, 0xfe,
+        0xff, 0xff, 0xb7, 0xbf, 0xf3, 0xb7, 0xff, 0xf5,
+        0xff, 0xff, 0xfe, 0xff, 0xaf, 0x2f, 0x77, 0xee,
+        0xf7, 0x5f, 0xee, 0xf7, 0xbf,
+        0xff, 0xff, 0xff, 0xff, 0xbf, 0xff, 0xe3, 0xea,
+        0x7f, 0xfa, 0xf5, 0x7f, 0xad, 0x7f, 0xff, 0xff,
+        0xff, 0x9d, 0x89, 0x7f, 0xf7,
+        0xff, 0xfd, 0x5b, 0x8e, 0xfc, 0xc0, 0x5f, 0xfb,
+        0xdf, 0x8f, 0x7f, 0x7a, 0x8a, 0x1f, 0xe0, 0x65,
+        0x6f, 0x6f, 0x5f, 0x8f, 0x7b,
+        0xbf, 0x7f, 0xd1, 0xbf, 0xcd, 0xf7, 0x2c, 0xbb,
+        0xb7, 0xf1, 0x8f, 0x7d, 0x92, 0x9f, 0xf0, 0xf7,
+        0xdf, 0xfd, 0xbf, 0xfb, 0x85,
+        0xff, 0xff, 0xbf, 0xff, 0x82, 0x7e, 0xf0, 0xfe,
+        0xfd, 0xf7, 0xff, 0xff, 0xbe, 0x7f, 0x8f, 0x7f,
+        0xe9, 0xfe, 0xff, 0xfc, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xbb, 0xff, 0x73, 0xdf,
+        0xef, 0x7f, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xf5, 0xeb, 0x4f, 0x7f, 0xff,
+        0xff, 0xff, 0xcf, 0xff, 0xbd, 0x7f, 0xb7, 0xff,
+        0xfd, 0xef, 0xfe, 0xff, 0xcf, 0xff, 0xf9, 0xf7,
+        0xfd, 0xff, 0xfd, 0xff, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xfa, 0xff, 0xff, 0xff,
+        0xfb, 0x0f, 0x0f, 0xf1, 0xd1, 0xff, 0xfd, 0xff,
+        0xbf, 0xdf, 0xff, 0x86, 0x0e,
+        0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xfb, 0xfe, 0xbf,
+        0x8b, 0x84, 0xf1, 0xf1, 0xff, 0xff, 0xf9, 0xbb,
+        0xfe, 0xaf, 0x0e, 0x07, 0x71,
+        0xbf, 0xf8, 0xf8, 0xff, 0x6a, 0xff, 0xfb, 0xff,
+        0xdf, 0x8f, 0xeb, 0xb3, 0xd7, 0xff, 0xf9, 0xbf,
+        0xf8, 0xff, 0xff, 0xaf, 0x2f,
+        0xff, 0xf8, 0x6f, 0xff, 0xff, 0xfe, 0xfe, 0xff,
+        0xef, 0xaf, 0xf7, 0xf5, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8e, 0x0f, 0x71,
+        0xff, 0xef, 0xef, 0xf5, 0xee, 0xff, 0xfe, 0xee,
+        0xff, 0xfa, 0xbf, 0xbb, 0xdd, 0xfb, 0xff, 0xdf,
+        0xbf, 0x99, 0xdf, 0xf9, 0xfb,
+        0xff, 0xfd, 0x6f, 0xfc, 0xef, 0xff, 0x9e, 0xef,
+        0xb5, 0xea, 0xbf, 0xaf, 0xdf, 0xfa, 0xff, 0xdf,
+        0xaf, 0x7f, 0xf6, 0xfb, 0xff,
+        0x7f, 0xf9, 0xee, 0xf7, 0xfe, 0xff, 0xfe, 0xff,
+        0xff, 0x8b, 0xfe, 0xb0, 0xda, 0xff, 0xff, 0xff,
+        0xbf, 0xff, 0xff, 0xc7, 0x7a,
+        0xbf, 0xfe, 0x7b, 0xff, 0xef, 0xff, 0xfe, 0xff,
+        0xff, 0xba, 0xcf, 0xfe, 0xf1, 0xfe, 0xff, 0xdf,
+        0xdf, 0xb9, 0xfc, 0xb9, 0xcf,
+        0xff, 0x95, 0x7e, 0xf3, 0xff, 0xff, 0xff, 0xfe,
+        0x9f, 0xff, 0xb1, 0xdf, 0xff, 0xf1, 0xff, 0xdf,
+        0xff, 0xbf, 0x8e, 0x5f, 0xb3,
+        0xff, 0xf8, 0x7d, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xdb, 0xff, 0xb0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xf9, 0xa9, 0x6f,
+        0x3f, 0xef, 0xfb, 0xff, 0x8f, 0x7f, 0xf0, 0xbe,
+        0xff, 0xff, 0x5e, 0x9f, 0x71, 0xf9, 0x8f, 0x5e,
+        0xf1, 0xbf, 0x7b, 0xd7, 0xbc,
+        0xff, 0x80, 0x7f, 0xf9, 0xff, 0x7f, 0xff, 0xff,
+        0xdb, 0x8f, 0x39, 0x90, 0xff, 0xf5, 0xff, 0xff,
+        0xff, 0xff, 0xf8, 0x8f, 0x7f,
+        0xff, 0x81, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xff, 0x9f, 0xc5, 0x7f, 0xf0, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xaf, 0x5f,
+        0xff, 0x7f, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xfe,
+        0x8f, 0x7b, 0xf0, 0xfb, 0xaf, 0xff, 0x89, 0xdf,
+        0xf7, 0xff, 0x89, 0x38, 0xf9,
+        0xff, 0xff, 0xff, 0xf7, 0xfe, 0x0f, 0xce, 0x84,
+        0xf8, 0xe0, 0xff, 0xbd, 0xaf, 0xff, 0xa9, 0xbe,
+        0x01, 0x47, 0x71, 0xd7, 0xfd,
+        0xff, 0xcb, 0xff, 0xff, 0xee, 0xff, 0xfe, 0xff,
+        0xef, 0xff, 0xff, 0xff, 0xaf, 0xf7, 0x9f, 0xfe,
+        0xf1, 0xf9, 0xef, 0xff, 0xf9,
+        0xbf, 0x87, 0xf8, 0xf8, 0xfe, 0x7f, 0xfe, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xb0, 0xf0, 0xaf, 0xff,
+        0xf7, 0xff, 0xff, 0xbf, 0x8f,
+        0xff, 0xdf, 0xff, 0xff, 0xfa, 0xff, 0xfe, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xa9, 0xff,
+        0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x7f, 0xff, 0xff, 0xfa, 0xff, 0xfe, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xaf, 0xff, 0xa9, 0xfe,
+        0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xfa, 0xff, 0xee, 0xff,
+        0xfa, 0xff, 0xff, 0xff, 0x9f, 0xff, 0x8f, 0xfe,
+        0xc7, 0xff, 0xf9, 0xbf, 0xff,
+        0xff, 0xff, 0x7f, 0xff, 0xfa, 0xff, 0xde, 0xff,
+        0xfd, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x9f, 0xff,
+        0xf7, 0x3e, 0xf7, 0xff, 0xff,
+        0xff, 0xdf, 0x1f, 0xbf, 0xf1, 0x86, 0xcf, 0xf0,
+        0xd7, 0xff, 0xfc, 0xff, 0x0f, 0x7f, 0xf9, 0xcb,
+        0x5f, 0xf1, 0xfe, 0xff, 0xff,
+        0xff, 0x7f, 0x7f, 0xb7, 0xff, 0xf7, 0x8f, 0xff,
+        0x00, 0xff, 0xf0, 0x7f, 0x2f, 0xdf, 0x7a, 0xff,
+        0x8f, 0x7f, 0x81, 0x7a, 0xb1,
+        0xff, 0xef, 0xcf, 0xd9, 0x99, 0x09, 0x74, 0xf4,
+        0xfb, 0x7f, 0x3f, 0xff, 0xcf, 0x7f, 0xb5, 0xbd,
+        0x7f, 0xf1, 0xf9, 0xff, 0xff,
+        0x7f, 0xbf, 0xc9, 0xbf, 0xfd, 0xe7, 0xbf, 0x9f,
+        0x55, 0x75, 0x7e, 0x87, 0xf9, 0xbf, 0x37, 0xd9,
+        0xff, 0xf5, 0xff, 0xff, 0x8e,
+        0xff, 0xe8, 0xf7, 0x9f, 0xfe, 0xa5, 0xfe, 0xf7,
+        0xff, 0xae, 0x75, 0xf0, 0x7f, 0xff, 0xff, 0xcf,
+        0x7e, 0xff, 0xff, 0x8b, 0x7f,
+        0xff, 0xff, 0x6f, 0xff, 0x8f, 0xef, 0xf0, 0x95,
+        0xff, 0xfb, 0xe7, 0x7f, 0xaf, 0xef, 0xab, 0x9b,
+        0xf1, 0xff, 0xd6, 0xfd, 0xff,
+        0xff, 0x97, 0x76, 0xa8, 0xee, 0xf7, 0xbf, 0xff,
+        0x77, 0x7f, 0xdf, 0xaf, 0xfe, 0xf1, 0xb7, 0xfb,
+        0xff, 0xff, 0xfe, 0xff, 0xff,
+        0xbf, 0xff, 0x51, 0xff, 0xb9, 0xb5, 0xe0, 0xff,
+        0x7f, 0xd7, 0xbf, 0xff, 0xa3, 0xef, 0x6d, 0x37,
+        0x71, 0xff, 0xdf, 0xff, 0xaf,
+        0xff, 0x7f, 0x07, 0xbf, 0xe8, 0xfb, 0xdc, 0xfd,
+        0xf7, 0xfe, 0xf7, 0xff, 0x8f, 0x7f, 0x99, 0xff,
+        0xfd, 0xef, 0xef, 0xfd, 0xff,
+        0xff, 0x7f, 0xbf, 0x7f, 0xdb, 0xff, 0xff, 0xfe,
+        0x3f, 0xff, 0xf5, 0x7f, 0xf7, 0x7f, 0xef, 0xff,
+        0xdb, 0xf9, 0xaf, 0x79, 0xff,
+        0xff, 0xf8, 0x1f, 0xdf, 0x90, 0x9c, 0x93, 0x95,
+        0xf4, 0x84, 0x7a, 0x70, 0xaf, 0x3f, 0x71, 0x7b,
+        0xfd, 0xff, 0xaf, 0x8f, 0x7d,
+        0xbf, 0x7f, 0xf0, 0xff, 0xfd, 0xdd, 0xff, 0xfe,
+        0x7d, 0xfe, 0xcf, 0x7f, 0xa0, 0xff, 0x76, 0xbf,
+        0xfb, 0xff, 0xdf, 0xf7, 0x8f,
+        0xff, 0xff, 0xbf, 0x7f, 0x83, 0xfe, 0xf0, 0xef,
+        0xff, 0x7b, 0xfa, 0xff, 0xff, 0xff, 0xe3, 0x7a,
+        0xf1, 0xdf, 0xff, 0xff, 0xff,
+        0x7f, 0x7f, 0xff, 0xf7, 0xcf, 0xfe, 0xf5, 0x9e,
+        0xff, 0x75, 0xfd, 0x7f, 0xff, 0xef, 0x48, 0xdf,
+        0xf1, 0xff, 0xef, 0xff, 0xfa,
+        0xff, 0xef, 0xcf, 0x7f, 0xcd, 0xf5, 0xef, 0xff,
+        0x79, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xcd, 0xf6,
+        0xdf, 0xff, 0xf7, 0xff, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xcf, 0xff,
+        0xdf, 0x0b, 0x2f, 0xf1, 0xb1, 0xff, 0xfd, 0xff,
+        0x8f, 0xff, 0xfd, 0xae, 0x2f,
+        0xff, 0xf8, 0x4f, 0xdf, 0x7e, 0xee, 0xdf, 0xbf,
+        0xaf, 0x89, 0xf1, 0xd1, 0xff, 0x8f, 0xdf, 0xed,
+        0xbe, 0xdf, 0x2c, 0x03, 0x51,
+        0xbf, 0xf1, 0xd9, 0xf7, 0x5e, 0xff, 0xf6, 0xff,
+        0xff, 0x8f, 0x9f, 0xe1, 0xb1, 0xff, 0x9d, 0xdf,
+        0xdc, 0xff, 0xff, 0xef, 0x7f,
+        0xff, 0xf8, 0x7e, 0xff, 0xff, 0xff, 0xf7, 0xff,
+        0x9f, 0x8f, 0xf0, 0xf0, 0xff, 0xdf, 0xcf, 0xff,
+        0xff, 0xff, 0xfe, 0x0f, 0x33,
+        0xff, 0xd7, 0xef, 0xfe, 0xef, 0xcf, 0xf7, 0xc6,
+        0xdf, 0xe6, 0xef, 0xc6, 0xdf, 0xf6, 0xce, 0xdf,
+        0xdf, 0x8f, 0xaf, 0xfd, 0xcc,
+        0xff, 0xc6, 0x7f, 0xfe, 0xef, 0xff, 0xbf, 0xcf,
+        0xf9, 0xde, 0xff, 0xcf, 0xff, 0xfe, 0xdf, 0xff,
+        0xff, 0x0f, 0xf2, 0x8d, 0xff,
+        0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8a, 0xee, 0xf8, 0xde, 0xff, 0xdf, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x7e,
+        0xbf, 0xef, 0x78, 0xff, 0xff, 0xcf, 0xf7, 0xc6,
+        0xf7, 0xf6, 0x8f, 0xf7, 0xf9, 0xf7, 0xcf, 0xff,
+        0xff, 0x8f, 0xfe, 0xdc, 0x8f,
+        0xff, 0x17, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0xcf, 0xf1, 0xbf, 0xff, 0xf1, 0xff, 0xdf,
+        0xff, 0xff, 0xaf, 0x7f, 0xf0,
+        0xff, 0xf8, 0xff, 0xff, 0xff, 0xff, 0xcf, 0xcf,
+        0xf6, 0x86, 0xcf, 0xf0, 0xf6, 0xff, 0xff, 0xdf,
+        0xff, 0xaf, 0xfe, 0x8d, 0x1f,
+        0x3f, 0xc6, 0xf8, 0xfe, 0x8f, 0x7f, 0xc0, 0xff,
+        0xfe, 0xf9, 0x3f, 0xcf, 0x79, 0xff, 0x8f, 0x5e,
+        0xf1, 0xff, 0x7f, 0xbe, 0xee,
+        0xff, 0x90, 0x7f, 0xf8, 0xff, 0x7f, 0xcf, 0xff,
+        0xd6, 0xaf, 0x6f, 0x88, 0xff, 0xf1, 0xff, 0xff,
+        0xaf, 0xff, 0xdc, 0x8f, 0x6f,
+        0xff, 0x81, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xbf, 0xcf, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+        0xff, 0xff, 0xbf, 0xff, 0x6d,
+        0xff, 0x7f, 0xcf, 0xff, 0xf7, 0xff, 0xcf, 0xcf,
+        0x1e, 0x56, 0xf0, 0xff, 0xdf, 0xff, 0xff, 0xdf,
+        0xff, 0xaf, 0x9f, 0x7d, 0xf1,
+        0xff, 0xfe, 0xcf, 0xf7, 0xc6, 0x3f, 0x86, 0xb9,
+        0xf0, 0xd0, 0xf7, 0xff, 0xdf, 0xff, 0xdf, 0xde,
+        0x0f, 0x83, 0x75, 0xf1, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xcf, 0xdf, 0xf6, 0xfe,
+        0xdf, 0xef, 0xff, 0xff, 0xdf, 0xff, 0xdf, 0xfe,
+        0xff, 0xff, 0xaf, 0xef, 0xfd,
+        0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x6f, 0xfe, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xd0, 0xf0, 0xdf, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xcf, 0xff, 0xc7, 0xff, 0xf6, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xcf, 0xff, 0xdd, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xcf, 0xf7, 0xc7, 0xff, 0xf6, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xcd, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f, 0xff, 0x9d, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xfe,
+        0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xbe, 0xcf,
+        0xf9, 0xf6, 0xff, 0xff, 0x9f, 0xff, 0x8d, 0xff,
+        0xff, 0x8e, 0xff, 0xfd, 0xff,
+        0xff, 0xff, 0x8f, 0x9f, 0xf2, 0x8e, 0xdf, 0xf8,
+        0xff, 0xff, 0xff, 0xff, 0x0f, 0x7f, 0x61, 0xaa,
+        0x7f, 0xf9, 0xcf, 0xff, 0xff,
+        0xff, 0x37, 0x9f, 0xe7, 0xfe, 0xf3, 0x0f, 0xcf,
+        0x00, 0xff, 0xc0, 0x7f, 0x7f, 0xcf, 0x7e, 0xfb,
+        0x8f, 0x7f, 0x80, 0x7f, 0xb1,
+        0xff, 0xeb, 0xef, 0xf9, 0xa9, 0x4f, 0x46, 0xf0,
+        0xf7, 0xff, 0x7f, 0xf7, 0xbf, 0xb8, 0xcd, 0x24,
+        0x33, 0xa3, 0xfd, 0xdf, 0xff,
+        0x3f, 0xfb, 0xf9, 0x5f, 0xf5, 0xfb, 0xff, 0xcf,
+        0xff, 0xff, 0xff, 0xaf, 0xe9, 0xb7, 0x7f, 0xa3,
+        0xdf, 0x7d, 0x73, 0xf3, 0xfe,
+        0xff, 0xc8, 0xe7, 0x3f, 0xee, 0xff, 0xd6, 0xf2,
+        0xff, 0xaf, 0x7f, 0xf8, 0x7f, 0xc7, 0x7e, 0xfb,
+        0x77, 0xd1, 0xff, 0x9f, 0x7f,
+        0xff, 0xff, 0x17, 0x9f, 0x96, 0xf6, 0xfc, 0x8f,
+        0xff, 0xdd, 0xff, 0x7f, 0x6f, 0xff, 0xb7, 0x7f,
+        0x71, 0x83, 0xf6, 0x7d, 0xf7,
+        0xff, 0xb7, 0x77, 0x90, 0xfd, 0xfe, 0xdf, 0xff,
+        0xbf, 0xfe, 0xbe, 0xcf, 0xff, 0xf8, 0x7f, 0xeb,
+        0xff, 0xf7, 0xdf, 0xff, 0xb7,
+        0xbf, 0xff, 0xf1, 0xff, 0xaf, 0xec, 0xf8, 0xff,
+        0xff, 0xfd, 0xef, 0xff, 0xb0, 0xef, 0x85, 0x7f,
+        0x79, 0xef, 0xbe, 0xfe, 0xef,
+        0xff, 0xff, 0x97, 0xaf, 0xda, 0xfb, 0xfe, 0xf3,
+        0xff, 0xff, 0xfe, 0xff, 0xcf, 0x1f, 0x69, 0xfb,
+        0xff, 0x77, 0xe6, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
+        0x97, 0xff, 0xfb, 0x7f, 0xf7, 0x7f, 0xdb, 0xff,
+        0xfd, 0xfd, 0xff, 0x7e, 0xf3,
+        0xff, 0xf8, 0x4f, 0x8f, 0xf0, 0xf6, 0x73, 0xff,
+        0xef, 0x9f, 0x7f, 0x70, 0x87, 0x0f, 0xf0, 0x75,
+        0x7b, 0x73, 0xd2, 0x9e, 0x7d,
+        0xbf, 0x7f, 0xf0, 0xbf, 0xcc, 0xfe, 0x37, 0xef,
+        0xff, 0xef, 0x8f, 0x7f, 0xc0, 0xcf, 0xb6, 0xff,
+        0xf5, 0x8f, 0xb7, 0xfd, 0x8f,
+        0xff, 0xff, 0x9f, 0xcf, 0x89, 0xff, 0xf0, 0x8f,
+        0xff, 0xfd, 0xff, 0x7f, 0xde, 0x3f, 0x89, 0x7d,
+        0xf1, 0x8e, 0xcf, 0xfd, 0xfd,
+        0x7f, 0xff, 0xff, 0xef, 0x8f, 0xe7, 0xf4, 0xff,
+        0xff, 0xff, 0xf6, 0x7f, 0xff, 0xbf, 0x8d, 0xef,
+        0xfd, 0xff, 0x7f, 0x73, 0xf6,
+        0xff, 0xff, 0xff, 0xef, 0x9e, 0xfc, 0xf7, 0xff,
+        0xfd, 0xff, 0xff, 0xff, 0xef, 0xaf, 0xd7, 0xff,
+        0x9f, 0xfe, 0xfd, 0xfe, 0xff,
+        0x3f, 0x78, 0xd8, 0xf7, 0xf7, 0xff, 0xdf, 0xbf,
+        0xff, 0x08, 0x0f, 0xf1, 0xf1, 0xff, 0xff, 0xff,
+        0xff, 0xef, 0xbf, 0x8e, 0x4e,
+        0xff, 0xd8, 0x7f, 0xff, 0x5f, 0xff, 0xf7, 0xaf,
+        0x8f, 0x8a, 0xf1, 0xf1, 0xdf, 0xdf, 0xff, 0xff,
+        0xfe, 0xaf, 0x4e, 0x01, 0x71,
+        0xbf, 0xf8, 0xd8, 0xf7, 0x77, 0xdf, 0xdf, 0xf7,
+        0xff, 0x8f, 0x8f, 0xf1, 0xd1, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0xff, 0x8f, 0x0f,
+        0xff, 0xf8, 0x7f, 0xdf, 0xdf, 0xf7, 0xd7, 0xff,
+        0xa7, 0x8f, 0xd1, 0xf1, 0xff, 0xff, 0xdf, 0xff,
+        0xff, 0xff, 0x8e, 0x0f, 0x71,
+        0xff, 0xef, 0xdf, 0xff, 0xd7, 0xdf, 0xf7, 0xd7,
+        0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xdf, 0xdf, 0xff, 0xff,
+        0xff, 0xef, 0x7f, 0xff, 0xdf, 0xff, 0xa7, 0xdf,
+        0xf8, 0xf7, 0xff, 0xd7, 0xff, 0xf7, 0xff, 0xff,
+        0xaf, 0x5f, 0xf0, 0xdf, 0xff,
+        0x7f, 0xf8, 0xdf, 0xf7, 0xd7, 0xff, 0xf7, 0xbf,
+        0xff, 0x89, 0xd7, 0xd0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xcf, 0xdf, 0x8f, 0x7e,
+        0xbf, 0xff, 0x78, 0xff, 0xdf, 0xff, 0xf7, 0xdf,
+        0xff, 0xd7, 0xaf, 0xd7, 0xf8, 0xf7, 0xff, 0xff,
+        0xff, 0xdf, 0xfe, 0xff, 0xaf,
+        0xff, 0x87, 0x7f, 0xf0, 0xff, 0xdf, 0xff, 0xf7,
+        0xaf, 0xff, 0xf0, 0xaf, 0xff, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0x8e, 0x7f, 0xf1,
+        0xff, 0xf8, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xf7,
+        0xff, 0x8f, 0xff, 0xf8, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xdf, 0xff, 0x8f, 0x7f,
+        0x3f, 0xd7, 0xf8, 0xff, 0x8f, 0x5f, 0xf0, 0xf7,
+        0xff, 0xf4, 0x0f, 0xff, 0x78, 0xff, 0x8f, 0x7e,
+        0xf1, 0xff, 0x7f, 0xf3, 0x8e,
+        0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xff, 0xaf, 0x7f, 0xa0, 0xff, 0xf1, 0xff, 0xff,
+        0xdf, 0xff, 0xae, 0x8f, 0x7f,
+        0xff, 0x80, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xaf, 0xff, 0x81, 0x7f, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0xff, 0x7f, 0xdf, 0xff, 0xf7, 0xdf, 0xdf, 0xf7,
+        0x87, 0x7f, 0xf0, 0xff, 0xdf, 0xff, 0xff, 0xfe,
+        0xff, 0xdf, 0x8f, 0x7e, 0xf1,
+        0xff, 0xff, 0xdf, 0xf7, 0xd7, 0x0f, 0x97, 0x80,
+        0xf0, 0xd0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xaf,
+        0x4f, 0xd1, 0x7e, 0xf1, 0xff,
+        0xff, 0xd7, 0xdf, 0xff, 0xd7, 0xff, 0xd7, 0xf7,
+        0x7f, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xdf, 0xff, 0xff,
+        0xbf, 0x87, 0xd8, 0xf8, 0xd7, 0x7f, 0xf7, 0xff,
+        0xff, 0xff, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xdf, 0xff, 0xd7, 0xff, 0xf7, 0xff,
+        0x7f, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xfe, 0xff,
+        0xff, 0xff, 0xdf, 0xf7, 0xd7, 0xff, 0xf7, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xdf, 0xff, 0xd7, 0xff, 0xf7, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xdf, 0xff, 0xd7, 0xff, 0xb7, 0xdf,
+        0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xef, 0xde, 0xff, 0xff, 0xff,
+        0xff, 0xfe, 0x0f, 0xaf, 0xd1, 0x8b, 0xf7, 0xf0,
+        0xff, 0xff, 0xff, 0x7f, 0x00, 0x2f, 0x71, 0xa1,
+        0x7f, 0xf1, 0xfe, 0xff, 0xff,
+        0xff, 0x7f, 0x3f, 0xe7, 0xfb, 0xfd, 0x0f, 0xff,
+        0x00, 0xff, 0xf0, 0x7f, 0xef, 0xbf, 0x7f, 0xf1,
+        0x8f, 0x7f, 0x81, 0x7e, 0xf1,
+        0xff, 0xa7, 0xff, 0xd9, 0x8c, 0x47, 0x73, 0xf4,
+        0xff, 0xff, 0x7f, 0x8f, 0xff, 0xd9, 0x8f, 0x1f,
+        0x71, 0xf0, 0xff, 0xdf, 0xff,
+        0x3f, 0xff, 0xf9, 0xee, 0xde, 0xfd, 0xe7, 0xee,
+        0x7f, 0xff, 0x8f, 0x7f, 0xf1, 0x9e, 0x7f, 0xe1,
+        0xbf, 0x3e, 0x71, 0xf1, 0x8e,
+        0xff, 0xf8, 0xd7, 0xaf, 0x77, 0x8b, 0xff, 0xf0,
+        0xff, 0xa7, 0x7f, 0xf0, 0x7f, 0xa7, 0x5f, 0x81,
+        0x7e, 0xf1, 0xbf, 0x0f, 0x71,
+        0xff, 0xff, 0xb7, 0xbf, 0x8b, 0xeb, 0xf2, 0xdf,
+        0xff, 0xff, 0xff, 0xff, 0xcf, 0xef, 0x8f, 0x3f,
+        0x71, 0xf1, 0xfe, 0x7f, 0xf7,
+        0xff, 0x87, 0xf7, 0xa8, 0xfe, 0xfb, 0xff, 0xff,
+        0xaf, 0xff, 0xfb, 0x8f, 0xf6, 0xa9, 0x7f, 0xd1,
+        0xff, 0x7f, 0xf6, 0xff, 0xff,
+        0xbf, 0xff, 0xd0, 0xd7, 0x87, 0xfe, 0xf0, 0xac,
+        0xff, 0xfb, 0xac, 0xff, 0xd9, 0xff, 0xaf, 0x7f,
+        0x71, 0xe3, 0xdf, 0x7f, 0x83,
+        0xff, 0xff, 0xa7, 0xaf, 0xf1, 0xa9, 0xff, 0xfb,
+        0xfd, 0xff, 0xfe, 0xff, 0xaf, 0x2f, 0x71, 0xe1,
+        0xff, 0xff, 0xef, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xbd, 0xff, 0xf3, 0xf7,
+        0x0f, 0xf7, 0xf8, 0x7f, 0xb7, 0x7f, 0xe1, 0xff,
+        0xff, 0xdf, 0xaf, 0x7f, 0xf1,
+        0xff, 0xf8, 0x4f, 0xbf, 0xe4, 0xeb, 0x65, 0xff,
+        0xff, 0x8f, 0x77, 0x70, 0x9f, 0x4f, 0xb1, 0x3f,
+        0x31, 0x31, 0x71, 0x81, 0x7f,
+        0xbf, 0x7f, 0xd0, 0xbf, 0xfe, 0xfb, 0x2f, 0xdf,
+        0xdb, 0xfe, 0x8f, 0x7f, 0xd0, 0xef, 0xdf, 0xff,
+        0xef, 0xef, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0x8f, 0xff, 0x80, 0xff, 0xf0, 0xdf,
+        0xff, 0xff, 0xff, 0xff, 0xaf, 0x7f, 0x81, 0x7f,
+        0xf1, 0x7f, 0xff, 0xff, 0xef,
+        0x7f, 0xff, 0xff, 0xff, 0x97, 0xff, 0xf2, 0xef,
+        0xef, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xef, 0xff,
+        0xff, 0xbf, 0x7f, 0x71, 0xf6,
+        0xff, 0xff, 0xff, 0xdf, 0xbf, 0xfe, 0xdb, 0xff,
+        0xfe, 0xff, 0xff, 0xff, 0xdf, 0xf7, 0xef, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0x3f, 0x78, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff,
+        0xff, 0xcf, 0xff, 0x8e, 0x0e,
+        0xff, 0xf8, 0x7f, 0xff, 0x7f, 0xff, 0xff, 0x8f,
+        0x8f, 0x00, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xfe, 0x8f, 0x0e, 0x01, 0x71,
+        0xbf, 0xf8, 0xf8, 0xf7, 0x7f, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff,
+        0xfe, 0xff, 0xff, 0x8f, 0x0f,
+        0xff, 0xf8, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x0f, 0x71, 0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8e, 0x0f, 0x71,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0x7f, 0x7f, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0x8f, 0xff,
+        0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x7f, 0xf0, 0xff, 0xff,
+        0x7f, 0xf8, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xcf, 0xff, 0x8f, 0x7e,
+        0xbf, 0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0xff, 0x8f,
+        0xff, 0x07, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0xff, 0xf0, 0x8f, 0xff, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0x8e, 0x7f, 0xf1,
+        0xff, 0x78, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0x3f, 0xff, 0x78, 0xff, 0x8f, 0x7f, 0xf0, 0x8f,
+        0xff, 0xf2, 0x8f, 0xff, 0xf0, 0xff, 0x8f, 0x7e,
+        0xf1, 0xbf, 0x7f, 0xf1, 0x8e,
+        0xff, 0x80, 0x7f, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0xff, 0x8f, 0x7f, 0x80, 0x7f, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0xfe, 0x8f, 0x7f,
+        0xff, 0x80, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0x8f, 0x7f, 0x81, 0x7f, 0xf0, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0xff, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x7f, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0x7f, 0xf1,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0x0f, 0xff, 0x80,
+        0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0x8e,
+        0x0f, 0x01, 0x71, 0xf1, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xdf, 0xff, 0xf7, 0xff, 0xff, 0xf5, 0xff, 0xfe,
+        0xff, 0xff, 0x9f, 0xff, 0xfc,
+        0xbf, 0x87, 0xf8, 0xf8, 0xff, 0x7f, 0xff, 0xff,
+        0x7f, 0x7f, 0x8f, 0x8f, 0xf0, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x7f, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x7f, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x8f, 0x7e, 0xf1, 0xff, 0xff,
+        0xbf, 0xff, 0x8a, 0x8f, 0xf0, 0x80, 0xff, 0xf0,
+        0xff, 0xff, 0xff, 0xff, 0x0f, 0x6f, 0xf1, 0x8f,
+        0x7f, 0xf1, 0xfe, 0xff, 0x8f,
+        0xff, 0x57, 0x7f, 0x8f, 0xff, 0xf0, 0x8f, 0xff,
+        0x00, 0xff, 0xf0, 0x5f, 0x6f, 0x97, 0x7f, 0xf1,
+        0x8f, 0x7f, 0x81, 0x7e, 0xd1,
+        0xff, 0xff, 0xff, 0xf8, 0x8f, 0x0f, 0x70, 0xf0,
+        0x8f, 0x7f, 0x70, 0xff, 0x9f, 0x79, 0xe1, 0x9f,
+        0x7f, 0xf1, 0x8f, 0x7f, 0xf1,
+        0x7f, 0xaf, 0xf8, 0x0f, 0xff, 0x78, 0x8f, 0x8f,
+        0x70, 0x70, 0x5f, 0xaf, 0xf1, 0x9e, 0x7f, 0xf0,
+        0xff, 0xff, 0xff, 0xff, 0xee,
+        0xff, 0xf8, 0xf7, 0x0f, 0xf7, 0x88, 0xf7, 0xf0,
+        0x8f, 0x8f, 0x70, 0xf0, 0x7e, 0xef, 0xff, 0x8f,
+        0x7e, 0xc1, 0xff, 0x8f, 0x7f,
+        0xff, 0x38, 0x77, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+        0xff, 0x0f, 0x77, 0x70, 0x6f, 0xef, 0xef, 0xff,
+        0xbf, 0xff, 0xff, 0x8f, 0x7f,
+        0xff, 0x87, 0x77, 0x88, 0xff, 0xf0, 0xff, 0xff,
+        0x77, 0x7f, 0xff, 0x8f, 0xfe, 0xe1, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xff,
+        0xbf, 0x7f, 0x70, 0xff, 0xff, 0x8f, 0xff, 0xf0,
+        0x0f, 0xfd, 0x82, 0xff, 0xf9, 0xff, 0xff, 0xbf,
+        0x7f, 0xe1, 0xbf, 0x7f, 0x81,
+        0xff, 0xff, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xf7, 0x7f, 0xf7, 0xff, 0xbf, 0xff, 0xbf, 0xef,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xf8, 0x77, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x0f, 0x8f, 0x70, 0x70, 0xf7, 0xff, 0xff, 0xff,
+        0xff, 0xcf, 0x8f, 0x1f, 0x71,
+        0xff, 0xf8, 0xff, 0x7f, 0xff, 0x8f, 0x8f, 0x80,
+        0x80, 0x80, 0x70, 0x70, 0x7f, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0x1f, 0x71,
+        0xbf, 0x7f, 0x70, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0x7f, 0xff, 0x8f, 0xff, 0x70, 0xff, 0xff, 0xff,
+        0xef, 0xff, 0xff, 0xef, 0x8f,
+        0xff, 0x07, 0x7f, 0x78, 0xfe, 0xff, 0xae, 0xff,
+        0xfb, 0x7f, 0xff, 0x0f, 0xff, 0xf0, 0xdf, 0xff,
+        0xff, 0xfe, 0xff, 0xfe, 0xff,
+        0x7f, 0x7f, 0xff, 0xff, 0xff, 0xff, 0xfe, 0x8f,
+        0xff, 0x70, 0xff, 0x7f, 0xff, 0xff, 0xcf, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0x7f, 0xf7, 0xff, 0xff, 0xfe, 0xff,
+        0x7f, 0x7f, 0xf7, 0xff, 0xdf, 0xff, 0xcf, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x77, 0x8f, 0x8f, 0xf0, 0xf0,
+        0xdf, 0xff, 0xf6, 0xff, 0xef, 0xef, 0x8f, 0x0f,
+        0x71, 0xb1, 0x3e, 0xf9, 0xf8,
+        0xff, 0xff, 0x7f, 0xff, 0x8f, 0x8f, 0xf0, 0xf0,
+        0xdf, 0xff, 0xf6, 0xff, 0xff, 0xef, 0xbf, 0x0f,
+        0x7d, 0xf1, 0x9e, 0xfe, 0xe9,
+        0xff, 0xdf, 0x7b, 0x72, 0x8f, 0xff, 0xf0, 0xbf,
+        0xff, 0xfa, 0xff, 0xef, 0xff, 0xfa, 0x8f, 0x7f,
+        0xf1, 0xbf, 0x7f, 0xf9, 0xff,
+        0xff, 0xfc, 0xfb, 0xff, 0xbf, 0xcf, 0xff, 0xe1,
+        0xaf, 0xdf, 0xfa, 0xf6, 0xff, 0xff, 0xff, 0xbf,
+        0x7f, 0xfd, 0xbe, 0xb7, 0xf5,
+        0xff, 0xf8, 0xff, 0xff, 0x8f, 0xff, 0xf0, 0xfe,
+        0xff, 0x8f, 0xff, 0xf8, 0xff, 0xff, 0x8f, 0x7f,
+        0xf1, 0x7f, 0xfb, 0x9f, 0xff,
+        0xff, 0xf8, 0x8b, 0x8f, 0xf0, 0xf0, 0xff, 0xcf,
+        0x7f, 0x8f, 0xff, 0xf8, 0x8f, 0x0f, 0x71, 0xf1,
+        0xff, 0x4f, 0x7b, 0x95, 0x7f,
+        0xff, 0xff, 0x8e, 0x7f, 0xf0, 0xff, 0xff, 0xff,
+        0xbf, 0xff, 0xfa, 0xff, 0x8f, 0x7f, 0xf1, 0xff,
+        0xfe, 0xff, 0xbf, 0xff, 0xbd,
+        0xff, 0xff, 0xff, 0x8f, 0x8f, 0xf0, 0x80, 0xff,
+        0xf0, 0xff, 0xff, 0xff, 0xff, 0x8f, 0x0f, 0x71,
+        0x81, 0x7f, 0xf1, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x87, 0xff, 0xf0, 0xff, 0xef,
+        0xbf, 0xbf, 0xff, 0xff, 0xff, 0x8f, 0x7f, 0xf1,
+        0xbf, 0x7f, 0x99, 0xd7, 0xfd,
+        0xff, 0xff, 0xf6, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xfe,
+        0xff, 0xff, 0xef, 0x77, 0xbf,
+        0xff, 0xce, 0xff, 0x88, 0xff, 0xf0, 0xef, 0xef,
+        0xfa, 0xdf, 0xff, 0xff, 0xff, 0x86, 0x7f, 0xd1,
+        0xff, 0xff, 0xf7, 0xb7, 0xff,
+        0xff, 0xff, 0xf7, 0xff, 0x8f, 0xff, 0xf0, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xf7, 0xff, 0x8f, 0x7e,
+        0xf1, 0xff, 0xff, 0xff, 0xef,
+        0xff, 0xf7, 0xff, 0xf7, 0xcf, 0x8f, 0xa8, 0xf0,
+        0xfa, 0xff, 0xff, 0xb7, 0xf7, 0xf7, 0x8f, 0x8f,
+        0x71, 0xf1, 0xf7, 0x77, 0xef,
+        0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0xff, 0xf0, 0xf7, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x6f,
+        0xbf, 0xff, 0xf0, 0xef, 0xff, 0xcf, 0xff, 0xf8,
+        0xff, 0xff, 0x8f, 0xff, 0xf0, 0x9f, 0xff, 0x8f,
+        0xff, 0xf1, 0xff, 0xff, 0x8f,
+        0xff, 0xff, 0xe7, 0xaf, 0xff, 0xf0, 0xff, 0xff,
+        0xff, 0xff, 0x7f, 0xbf, 0x9f, 0x9f, 0x7f, 0xf9,
+        0xff, 0xfe, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0x7f,
+        0xff, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0x7f,
+        0xbf, 0xff, 0xf7, 0xcf, 0xff, 0xf8, 0xff, 0x7f,
+        0x9f, 0xff, 0xf1, 0xff, 0xff, 0x8f, 0xff, 0xf1,
+        0xff, 0xff, 0xdf, 0xff, 0xe1,
+        0xff, 0xff, 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0xff, 0xf0, 0xff, 0xfe, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0x9f,
+        0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xfe,
+        0xff, 0xff, 0xff, 0xef, 0xff,
+        0xff, 0xf8, 0xff, 0xf7, 0xbf, 0xff, 0xf7, 0xff,
+        0xff, 0x8f, 0xff, 0xf0, 0xff, 0xff, 0xff, 0x7f,
+        0xff, 0xff, 0xff, 0x9f, 0xff,
+        0xff, 0xf8, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0x8f, 0xef, 0xf0, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0x8f, 0x7f,
+        0xff, 0xff, 0xf7, 0xff, 0x0f, 0xfe, 0xf0, 0xff,
+        0xff, 0xef, 0xff, 0xef, 0xff, 0xcf, 0x8f, 0x7f,
+        0xf1, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+        0xff, 0xef, 0x7f, 0xff, 0xff,
+        0xff, 0xff, 0x8f, 0xff, 0xf1, 0xff, 0xff, 0xff,
+        0xff, 0xff, 0xef, 0xff, 0xbf, 0x7f, 0xf1, 0xff,
+        0xbf, 0xff, 0xff, 0xff, 0xbf,
+        0xff, 0xa7, 0xff, 0x88, 0xff, 0xf1, 0xfe, 0xff,
+        0xff, 0xff, 0xff, 0x1f, 0xff, 0xf0, 0xcf, 0xf1,
+        0xff, 0xff, 0xff, 0xbf, 0xff,

diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c
index 9d963c12ab67c8f30465c4e5a4919a9a1e5604f5..531223ef2b06bc530571e2b28719b03b0a11c00d 100644 (file)
--- a/board/sixnet/sixnet.c
+++ b/board/sixnet/sixnet.c
@@ -1,9 +1,10 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2001, 2002
+ * Dave Ellis, SIXNET, dge@sixnetio.com.
+ *  Based on code by:
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
+ * and other contributors to PPCBoot. See file CREDITS for list
+ * of people who contributed to this  project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -23,171 +24,17 @@
 
 #include <ppcboot.h>
 #include <config.h>
-#include "mpc8xx.h"
+#include <mpc8xx.h>
+#include <net.h>       /* for eth_init() */
+#include <rtc.h>
 #include "sixnet.h"
 
-/* ------------------------------------------------------------------------- */
+#define ORMASK(size) ((-size) & OR_AM_MSK)
 
-#define        _NOT_USED_      0xFFFFFFFF
-
-#if defined(CONFIG_DRAM_50MHZ)
-/* 50MHz tables */
-const uint dram_60ns[] =
-{ 0x8fffec24, 0x0fffec04, 0x0cffec04, 0x00ffec04,
-  0x00ffec00, 0x37ffec47, 0xffffffff, 0xffffffff,
-  0x8fffec24, 0x0fffec04, 0x08ffec04, 0x00ffec0c,
-  0x03ffec00, 0x00ffec44, 0x00ffcc08, 0x0cffcc44,
-  0x00ffec0c, 0x03ffec00, 0x00ffec44, 0x00ffcc00,
-  0x3fffc847, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
-  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint dram_70ns[] =
-{ 0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
-  0x00ffcc00, 0x37ffcc47, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0fffcc04, 0x0cffcc04, 0x00ffcc04,
-  0x00ffcc08, 0x0cffcc44, 0x00ffec0c, 0x03ffec00,
-  0x00ffec44, 0x00ffcc08, 0x0cffcc44, 0x00ffec04,
-  0x00ffec00, 0x3fffec47, 0xffffffff, 0xffffffff,
-  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x11bfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fafcc24, 0x0fafcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
-  0x7fffcc06, 0xffffcc85, 0xffffcc05, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint edo_60ns[] =
-{ 0x8ffbec24, 0x0ff3ec04, 0x0cf3ec04, 0x00f3ec04,
-  0x00f3ec00, 0x37f7ec47, 0xffffffff, 0xffffffff,
-  0x8fffec24, 0x0ffbec04, 0x0cf3ec04, 0x00f3ec0c,
-  0x0cf3ec00, 0x00f3ec4c, 0x0cf3ec00, 0x00f3ec4c,
-  0x0cf3ec00, 0x00f3ec44, 0x03f3ec00, 0x3ff7ec47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc4f, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xc0ffcc84, 0x00ffcc04, 0x07ffcc04, 0x3fffcc06,
-  0xffffcc85, 0xffffcc05, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint edo_70ns[] =
-{ 0x8ffbcc24, 0x0ff3cc04, 0x0cf3cc04, 0x00f3cc04,
-  0x00f3cc00, 0x37f7cc47, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc0c,
-  0x03f3cc00, 0x00f3cc44, 0x00f3ec0c, 0x0cf3ec00,
-  0x00f3ec4c, 0x03f3ec00, 0x00f3ec44, 0x00f3cc00,
-  0x33f7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x11bfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x8fffcc24, 0x0fefcc04, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x03afcc4c, 0x0cafcc00, 0x03afcc4c,
-  0x0cafcc00, 0x33bfcc47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xe0ffcc84, 0x00ffcc04, 0x00ffcc04, 0x0fffcc04,
-  0x7fffcc04, 0xffffcc86, 0xffffcc05, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-#elif defined(CONFIG_DRAM_25MHZ)
-
-/* 25MHz tables */
-
-const uint dram_60ns[] =
-{ 0x0fffcc04, 0x08ffcc00, 0x33ffcc47, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
-  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
-  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
-  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
-  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint dram_70ns[] =
-{ 0x0fffec04, 0x08ffec04, 0x00ffec00, 0x3fffcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fffcc24, 0x0fffcc04, 0x08ffcc00, 0x03ffcc4c,
-  0x08ffcc00, 0x03ffcc4c, 0x08ffcc00, 0x03ffcc4c,
-  0x08ffcc00, 0x33ffcc47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fafcc04, 0x08afcc00, 0x3fbfcc47, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fafcc04, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
-  0x01afcc4c, 0x0cafcc00, 0x01afcc4c, 0x0cafcc00,
-  0x31bfcc43, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint edo_60ns[] =
-{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0ffbcc04, 0x09f3cc0c, 0x09f3cc0c, 0x09f3cc0c,
-  0x08f3cc00, 0x3ff7cc47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fefcc04, 0x08afcc00, 0x07afcc48, 0x08afcc48,
-  0x08afcc48, 0x39bfcc47, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x80ffcc84, 0x13ffcc04, 0xffffcc87, 0xffffcc05,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-const uint edo_70ns[] =
-{ 0x0ffbcc04, 0x0cf3cc04, 0x00f3cc00, 0x33f7cc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0ffbec04, 0x08f3ec04, 0x03f3ec48, 0x08f3cc00,
-  0x0ff3cc4c, 0x08f3cc00, 0x0ff3cc4c, 0x08f3cc00,
-  0x3ff7cc47, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fefcc04, 0x08afcc04, 0x00afcc00, 0x3fbfcc47,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x0fefcc04, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
-  0x07afcc4c, 0x08afcc00, 0x07afcc4c, 0x08afcc00,
-  0x37bfcc47, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xc0ffcc84, 0x01ffcc04, 0x7fffcc86, 0xffffcc05,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-  0x33ffcc07, 0xffffffff, 0xffffffff, 0xffffffff };
-
-
-#else
-#error dram not correct defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
-#endif
+static long ram_size(ulong *, long);
 
 /* ------------------------------------------------------------------------- */
 
-
 /*
  * Check Board Identity:
  * returns 0 if recognized, -1 if unknown
@@ -195,208 +42,314 @@ const uint edo_70ns[] =
 
 int checkboard (void)
 {
-       uint k;
-
-       k = (*((uint *)BCSR3) >> 24) & 0x3f;
-
-       switch(k)
-       {
-               case 0x22 :
-                       printf("FADS simulating SIXNET SXNI855T\n");
-                       break;
-
-               case 0xff :
-                       printf("SIXNET SXNI855T");
-                       break;
-
-               default :
-                       printf("unknown board (0x%02x)\n", k);
-                       return -1;
-       }
+       printf("SIXNET SXNI855T\n");
 
        return 0;
 }
 
 /* ------------------------------------------------------------------------- */
-int _draminit(uint base, uint noMbytes, uint edo, uint delay)
-{
-       volatile immap_t     *immap = (immap_t *)CFG_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-       /* init upm */
+#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
+#error "SXNI855T has no PCMCIA port"
+#endif /* CFG_CMD_PCMCIA */
 
-       switch(delay)
-       {
-               case 70:
-               {
-                       if(edo)
-                       {
-                               upmconfig(UPMA, (uint *) edo_70ns, sizeof(edo_70ns)/sizeof(uint));
-                       }
-                       else
-                       {
-                               upmconfig(UPMA, (uint *) dram_70ns, sizeof(dram_70ns)/sizeof(uint));
-                       }
-
-                       break;
-               }
-
-               case 60:
-               {
-                       if(edo)
-                       {
-                               upmconfig(UPMA, (uint *) edo_60ns, sizeof(edo_60ns)/sizeof(uint));
-                       }
-                       else
-                       {
-                               upmconfig(UPMA, (uint *) dram_60ns, sizeof(dram_60ns)/sizeof(uint));
-                       }
-
-                       break;
-               }
-
-               default :
-                       return -1;
-       }
+/* ------------------------------------------------------------------------- */
 
-       memctl->memc_mptpr = 0x0400; /* divide by 16 */
+#define _not_used_ 0xffffffff
 
-       switch(noMbytes)
-       {
+/* UPMB table for dual UART. */
 
-               case 8:  /* 8 Mbyte uses both CS3 and CS2 */
-               {
-                       memctl->memc_mamr = 0x13a01114;
-                       memctl->memc_or3 = 0xffc00800;
-                       memctl->memc_br3 = 0x00400081 + base;
-                       memctl->memc_or2 = 0xffc00800;
-                       break;
-               }
-
-               case 4: /* 4 Mbyte uses only CS2 */
-               {
-                       memctl->memc_mamr = 0x13a01114;
-                       memctl->memc_or2 = 0xffc00800;
-                       break;
-               }
-
-               case 32: /* 32 Mbyte uses both CS3 and CS2 */
-               {
-                       memctl->memc_mamr = 0x13b01114;
-                       memctl->memc_or3 = 0xff000800;
-                       memctl->memc_br3 = 0x01000081 + base;
-                       memctl->memc_or2 = 0xff000800;
-                       break;
-               }
-
-               case 16: /* 16 Mbyte uses only CS2 */
-               {
-#ifdef CONFIG_ADS
-                       memctl->memc_mamr = 0x60b21114;
-#else
-                       memctl->memc_mamr = 0x13b01114;
-#endif
-                       memctl->memc_or2 = 0xff000800;
-                       break;
-               }
+/* this table is for 50MHz operation, it should work at all lower speeds */
+const uint duart_table[] =
+{
+       /* single read. (offset 0 in upm RAM) */
+       0xfffffc04, 0x0ffffc04, 0x0ff3fc04, 0x0ff3fc04,
+       0x0ff3fc00, 0x0ff3fc04, 0xfffffc04, 0xfffffc05,
 
-               default:
-                   return -1;
-       }
+       /* burst read. (offset 8 in upm RAM) */
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
 
-       memctl->memc_br2 = 0x81 + base;     /* use upma */
-       return 0;
-}
+       /* single write. (offset 18 in upm RAM) */
+       0xfffffc04, 0x0ffffc04, 0x00fffc04, 0x00fffc04,
+       0x00fffc04, 0x00fffc00, 0xfffffc04, 0xfffffc05,
 
-/* ------------------------------------------------------------------------- */
+       /* burst write. (offset 20 in upm RAM) */
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+
+       /* refresh. (offset 30 in upm RAM) */
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
+       _not_used_, _not_used_, _not_used_, _not_used_,
 
-void _dramdisable(void)
+       /* exception. (offset 3c in upm RAM) */
+       _not_used_, _not_used_, _not_used_, _not_used_,
+};
+
+/* Load FPGA very early in boot sequence, since it must be
+ * loaded before the 16C2550 serial channels can be used as
+ * console channels.
+ *
+ * Note: Much of the configuration is not complete. The
+ *       stack is in DPRAM since SDRAM has not been initialized,
+ *       so the stack must be kept small. Global variables
+ *       are still in FLASH, so they cannot be written.
+ *      Only the FLASH, DPRAM, immap and FPGA can be addressed,
+ *       the other chip selects may not have been initialized.
+ *       The clocks have been initialized, so udelay() can be
+ *       used.
+ */
+void board_postclk_init (void)
 {
+#define FPGA_DONE      0x0080  /* PA8, input, high when FPGA load complete */
+#define FPGA_PROGRAM_L 0x0040  /* PA9, output, low to reset, high to start */
+#define FPGA_INIT_L    0x0020  /* PA10, input, low indicates not ready */
+#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))      /* FPGA port */
+
+       /* the data to load to the XCSxxXL FPGA */
+       static const unsigned char fpgadata[] = {
+               #include "fpgadata.c"
+       };
+
        volatile immap_t     *immap = (immap_t *)CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
+#define porta (immap->im_ioport.iop_padat)
+       const unsigned char* pdata;
 
-       memctl->memc_br2 = 0x00000000;
-       memctl->memc_br3 = 0x00000000;
+       /* /INITFPGA and DONEFPGA signals are inputs */
+       immap->im_ioport.iop_padir &= ~(FPGA_INIT_L | FPGA_DONE);
 
-       /* maybe we should turn off upma here or something */
-}
+       /* Force output pin to begin at 0, /PROGRAM asserted (0) resets FPGA */
+       porta &= ~FPGA_PROGRAM_L;
 
-#if defined(CONFIG_SDRAM_100MHZ)
+       /* Set FPGA as an output */
+       immap->im_ioport.iop_padir |= FPGA_PROGRAM_L;
 
-/* ------------------------------------------------------------------------- */
-/* sdram table by Dan Malek                                                  */
+       /* delay a little to make sure FPGA sees it, really
+        * only need less than a microsecond.
+        */
+       udelay(10);
 
-/* This has the stretched early timing so the 50 MHz
- * processor can make the 100 MHz timing.  This will
- * work at all processor speeds.
- */
+       /* unassert /PROGRAM */
+       porta |= FPGA_PROGRAM_L;
 
-#define SDRAM_MPTPRVALUE 0x0400
+       /* delay while FPGA does last erase, indicated by
+        * /INITFPGA going high. This should happen within a
+        * few milliseconds.
+        */
+       /* ### FIXME - a timeout check would be good, maybe flash
+        * the status LED to indicate the error?
+        */
+       while ((porta & FPGA_INIT_L) == 0)
+               ; /* waiting */
 
-#define SDRAM_MBMRVALUE0 0xc3802114  /* (16-14) 50 MHz */
-#define SDRAM_MBMRVALUE1 SDRAM_MBMRVALUE0
+       /* write program data to FPGA at the programming address
+        * so extra /CS1 strobes at end of configuration don't actually
+         * write to any registers.
+        */
+       fpga = 0xff;            /* first write is ignored       */
+       fpga = 0xff;            /* fill byte                    */
+       fpga = 0xff;            /* fill byte                    */
+       fpga = 0x4f;            /* preamble code                */
+       fpga = 0x80; fpga = 0xaf; fpga = 0x9b; /* length (ignored) */
+       fpga = 0x4b;            /* field check code */
+
+       pdata = fpgadata;
+       /* while no error write out each of the 28 byte frames */
+       while ((porta & (FPGA_INIT_L | FPGA_DONE)) == FPGA_INIT_L
+              && pdata < fpgadata + sizeof(fpgadata)) {
+
+               fpga = 0x4f;    /* preamble code */
+
+               /* 21 bytes of data in a frame */
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++); fpga = *(pdata++);
+               fpga = *(pdata++);
+
+               fpga = 0x4b;    /* field check code             */
+               fpga = 0xff;    /* extended write cycle         */
+               fpga = 0x4b;    /* extended write cycle
+                                * (actually 0x4b from bitgen.exe)
+                                */
+               fpga = 0xff;    /* extended write cycle         */
+               fpga = 0xff;    /* extended write cycle         */
+               fpga = 0xff;    /* extended write cycle         */
+       }
 
-#define SDRAM_OR4VALUE   0xffc00a00
-#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */
+       fpga = 0xff;            /* startup byte                 */
+       fpga = 0xff;            /* startup byte                 */
+       fpga = 0xff;            /* startup byte                 */
+       fpga = 0xff;            /* startup byte                 */
+
+#if 0 /* ### FIXME */
+       /* If didn't load all the data or FPGA_DONE is low the load failed.
+        * Maybe someday stop here and flash the status LED? The console
+        * is not configured, so can't print an error message. Can't write
+        * global variables to set a flag (except idata?).
+        * For now it must work.
+        */
+#endif
 
-#define SDRAM_MARVALUE   0x88
+       /* Now that the FPGA is loaded, set up the Dual UART chip
+        * selects. Must be done here since it may be used as the console.
+        */
+       upmconfig(UPMB, (uint *)duart_table, sizeof(duart_table)/sizeof(uint));
 
-#define SDRAM_MCRVALUE0  0x80808111   /* run pattern 0x11 */
-#define SDRAM_MCRVALUE1  SDRAM_MCRVALUE0
+       memctl->memc_mbmr = DUART_MBMR;
+       memctl->memc_or5 = DUART_OR_VALUE;
+       memctl->memc_br5 = DUART_BR5_VALUE;
+       memctl->memc_or6 = DUART_OR_VALUE;
+       memctl->memc_br6 = DUART_BR6_VALUE;
 
+       
+}
 
-const uint sdram_table[] =
+/* ------------------------------------------------------------------------- */
+
+/* base address for SRAM, assume 32-bit port,  valid */
+#define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+
+/*  up to 64MB - will be adjusted for actual size */
+#define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
+       | OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+/*
+ * Miscellaneous platform dependent initializations after running in RAM.
+ */
+
+void misc_init_r(bd_t *bd)
 {
-       /* single read. (offset 0 in upm RAM) */
-       0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x11adfc04,
-       0xefbbbc00, 0x1ff77c45, 0xffffffff, 0xffffffff,
+       volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+       volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-       /* burst read. (offset 8 in upm RAM) */
-       0xefebfc24, 0x1f07fc24, 0xeeaefc04, 0x10adfc04,
-       0xf0affc00, 0xf0affc00, 0xf1affc00, 0xefbbbc00,
-       0x1ff77c45, 0xeffbbc04, 0x1ff77c34, 0xefeabc34,
-       0x1fb57c35, 0xffffffff, 0xffffffff, 0xffffffff,
+       memctl->memc_or2 = NVRAM_OR_PRELIM;
+       memctl->memc_br2 = NVRAM_BR_VALUE;
 
-       /* single write. (offset 18 in upm RAM) */
-       0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x01b93c04,
-       0x1ff77c45, 0xffffffff, 0xffffffff, 0xffffffff,
+       /* Is there any SRAM? Is it 16 or 32 bits wide? */
 
-       /* burst write. (offset 20 in upm RAM) */
-       0xefebfc24, 0x1f07fc24, 0xeeaebc00, 0x10ad7c00,
-       0xf0affc00, 0xf0affc00, 0xe1bbbc04, 0x1ff77c45,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       /* First look for 32-bit SRAM */
+       bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
 
-       /* refresh. (offset 30 in upm RAM) */
-       0xeffafc84, 0x1ff5fc04, 0xfffffc04, 0xfffffc04,
-       0xfffffc84, 0xfffffc07, 0xffffffff, 0xffffffff,
-       0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
+       if (bd->bi_sramsize == 0) {
+           /* no 32-bit SRAM, but there could be 16-bit SRAM since
+            * it would report size 0 when configured for 32-bit bus.
+            * Try again with a 16-bit bus.
+            */
+           memctl->memc_br2 |= BR_PS_16;
+           bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+       }
 
-       /* exception. (offset 3c in upm RAM) */
-       0xeffffc06, 0x1ffffc07, 0xffffffff, 0xffffffff };
+       if (bd->bi_sramsize == 0) {
+           memctl->memc_br2 = 0;       /* disable select since nothing there */
+       }
+       else {
+           /* adjust or2 for actual size of SRAM */
+           memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
+           bd->bi_sramstart = CFG_SRAM_BASE;
+           printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
+       }
 
-#elif defined(CONFIG_SDRAM_50MHZ)
 
-/* ------------------------------------------------------------------------- */
-/* sdram table stolen from the fads manual                                   */
-/* for chip MB811171622A-100                                                 */
+       /* set standard MPC8xx clock so kernel will see the time
+        * even if it doesn't have a DS1306 clock driver.
+        * This helps with experimenting with standard kernels.
+        */
+       {
+           ulong tim;
+           struct rtc_time tmp;
 
-/* this table is for 32-50MHz operation */
+           rtc_get(&tmp);      /* get time from DS1306 RTC */
 
-#define _not_used_ 0xffffffff
+           /* convert to seconds since 1970 */
+           tim = mktime(tmp.tm_year, tmp.tm_mon, tmp.tm_mday,
+                        tmp.tm_hour, tmp.tm_min, tmp.tm_sec);
 
-#define SDRAM_MPTPRVALUE 0x0400
+           immap->im_sitk.sitk_rtck = KAPWR_KEY;
+           immap->im_sit.sit_rtc = tim;
+       }
 
-#define SDRAM_MBMRVALUE0 0x80802114   /* refresh at 32MHz */
-#define SDRAM_MBMRVALUE1 0x80802118
+       /* FIXME - for now init ethernet to force PHY special mode */
+       eth_init(bd);
+       eth_halt();
+}
 
-#define SDRAM_OR4VALUE   0xffc00a00
-#define SDRAM_BR4VALUE   0x000000c1   /* base address will be or:ed on */
+/* ------------------------------------------------------------------------- */
 
-#define SDRAM_MARVALUE   0x88
+/*
+ * Check memory range for valid RAM. A simple memory test determines
+ * the actually available RAM size between addresses `base' and
+ * `base + maxsize'.
+ *
+ * The memory size MUST be a power of 2 for this to work.
+ *
+ * The only memory modified is 4 bytes at offset 0. This is important
+ * since for the SRAM this location is reserved for autosizing, so if
+ * it is modified and the board is reset before ram_size() completes
+ * no damage is  done. Normally even the memory at 0 is preserved. The
+ * higher SRAM addresses may contain battery backed RAM disk data which
+ * must never be corrupted.
+ */
+
+static long ram_size(ulong *base, long maxsize)
+{
+    volatile long      *test_addr;
+    volatile long      *base_addr = base;
+    volatile long      *flash = (volatile long*)CFG_FLASH_BASE;
+    ulong              ofs;            /* byte offset from base_addr */
+    ulong              save;           /* to make test non-destructive */
+    ulong              junk;
+    long               ramsize = -1;   /* size not determined yet */
+
+    save = *base_addr;         /* save value at 0 so can restore */
+
+    /* is any SRAM present? */
+    *base_addr = 0x5555aaaa;
+
+    /* use flash read to modify data bus, since with no SRAM present
+     * the data bus may retain the value if our code is running
+     * completely in the cache.
+     */
+    junk = *flash;     
+
+    if (*base_addr != 0x5555aaaa)
+       ramsize = 0;            /* no RAM present, or defective */      
+    else {
+       *base_addr = 0xaaaa5555;
+       junk = *flash;          /* use flash read to modify data bus */
+       if (*base_addr != 0xaaaa5555)
+           ramsize = 0;        /* no RAM present, or defective */      
+    }
+    
+    /* now size it if any is present */
+    for (ofs = 4; ofs < maxsize && ramsize < 0; ofs <<= 1) {
+       test_addr = (long*)((long)base_addr + ofs);     /* location to test */
+
+       *base_addr = ~*test_addr;
+       if (*base_addr == *test_addr)
+           ramsize = ofs;      /* wrapped back to 0, so this is the size */
+    }
+
+    *base_addr = save;         /* restore value at 0 */
+    return (ramsize);
+}
+
+/* ------------------------------------------------------------------------- */
+/* sdram table based on the FADS manual                                      */
+/* for chip MB811171622A-100                                                 */
 
-#define SDRAM_MCRVALUE0  0x80808105
-#define SDRAM_MCRVALUE1  0x80808130
+/* this table is for 50MHz operation, it should work at all lower speeds */
 
 const uint sdram_table[] =
 {
@@ -404,8 +357,10 @@ const uint sdram_table[] =
        0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
        0x1ff77c47,
 
-       /* MRS initialization (offset 5) */
-
+       /* precharge and Mode Register Set initialization (offset 5).
+        * This is also entered at offset 6 to do Mode Register Set
+        * without the precharge.
+        */
        0x1ff77c34, 0xefeabc34, 0x1fb57c35,
 
        /* burst read. (offset 8 in upm RAM) */
@@ -415,7 +370,13 @@ const uint sdram_table[] =
        _not_used_, _not_used_, _not_used_, _not_used_,
 
        /* single write. (offset 18 in upm RAM) */
-       0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
+        /* FADS had 0x1f27fc04, ...
+        * but most other boards have 0x1f07fc04, which
+        * sets GPL0 from A11MPC to 0 1/4 clock earlier,
+        * like the single read.
+        * This seems better so I am going with the change.
+        */
+       0x1f07fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47,
        _not_used_, _not_used_, _not_used_, _not_used_,
 
        /* burst write. (offset 20 in upm RAM) */
@@ -433,225 +394,157 @@ const uint sdram_table[] =
        0x7ffffc07, _not_used_, _not_used_, _not_used_ };
 
 /* ------------------------------------------------------------------------- */
-#else
-#error SDRAM not correctly configured
-#endif
-
-int _initsdram(uint base, uint noMbytes)
-{
-       volatile immap_t     *immap = (immap_t *)CFG_IMMR;
-       volatile memctl8xx_t *memctl = &immap->im_memctl;
-
-       if(noMbytes != 4)
-       {
-               return -1;
-       }
-
-       upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
-
-       memctl->memc_mptpr = SDRAM_MPTPRVALUE;
-
-       /* Configure the refresh (mostly).  This needs to be
-       * based upon processor clock speed and optimized to provide
-       * the highest level of performance.  For multiple banks,
-       * this time has to be divided by the number of banks.
-       * Although it is not clear anywhere, it appears the
-       * refresh steps through the chip selects for this UPM
-       * on each refresh cycle.
-       * We have to be careful changing
-       * UPM registers after we ask it to run these commands.
-       */
-
-       memctl->memc_mbmr = SDRAM_MBMRVALUE0;
-       memctl->memc_mar = SDRAM_MARVALUE;  /* MRS code */
-
-       udelay(200);
-
-       /* Now run the precharge/nop/mrs commands.
-       */
-
-       memctl->memc_mcr = 0x80808111;   /* run pattern 0x11 */
-
-       udelay(200);
-
-       /* Run 8 refresh cycles */
 
-       memctl->memc_mcr = SDRAM_MCRVALUE0;
-
-       udelay(200);
-
-       memctl->memc_mbmr = SDRAM_MBMRVALUE1;
-       memctl->memc_mcr = SDRAM_MCRVALUE1;
-
-       udelay(200);
-
-       memctl->memc_mbmr = SDRAM_MBMRVALUE0;
-
-       memctl->memc_or4 = SDRAM_OR4VALUE;
-       memctl->memc_br4 = SDRAM_BR4VALUE | base;
-
-       return 0;
-}
+#define        SDRAM_MAX_SIZE          0x10000000      /* max 256 MB SDRAM */
+
+/* precharge and set Mode Register */
+#define SDRAM_MCR_PRE    (MCR_OP_RUN | MCR_UPM_A |     /* select UPM     */ \
+                         MCR_MB_CS3 |                  /* chip select    */ \
+                         MCR_MLCF(1) | MCR_MAD(5))     /* 1 time at 0x05 */
+
+/* set Mode Register, no precharge */
+#define SDRAM_MCR_MRS    (MCR_OP_RUN | MCR_UPM_A |     /* select UPM     */ \
+                         MCR_MB_CS3 |                  /* chip select    */ \
+                         MCR_MLCF(1) | MCR_MAD(6))     /* 1 time at 0x06 */
+
+/* runs refresh loop twice so get 8 refresh cycles */
+#define SDRAM_MCR_REFR   (MCR_OP_RUN | MCR_UPM_A |     /* select UPM     */ \
+                         MCR_MB_CS3 |                  /* chip select    */ \
+                         MCR_MLCF(2) | MCR_MAD(0x30))  /* twice at 0x30  */
+
+/* MAMR values work in either mamr or mbmr */
+/* 8 column SDRAM */
+#define SDRAM_MAMR_8COL  /* refresh at 50MHz */                                  \
+                        ((195 << MAMR_PTA_SHIFT) | MAMR_PTAE             \
+                        | MAMR_AMA_TYPE_0      /* Address MUX 0 */       \
+                        | MAMR_DSA_1_CYCL      /* 1 cycle disable */     \
+                        | MAMR_G0CLA_A11       /* GPL0 A11[MPC] */       \
+                        | MAMR_RLFA_1X         /* Read loop 1 time */    \
+                        | MAMR_WLFA_1X         /* Write loop 1 time */   \
+                        | MAMR_TLFA_4X)        /* Timer loop 4 times */
+
+/* 9 column SDRAM */
+#define SDRAM_MAMR_9COL ((SDRAM_MAMR_8COL & (~MAMR_G0CLA_A11)) | MAMR_G0CLA_A10)
+
+/* base address 0, 32-bit port, SDRAM UPM, valid */
+#define SDRAM_BR_VALUE   (BR_PS_32 | BR_MS_UPMA | BR_V)
+
+/*  up to 256MB, SAM, G5LS - will be adjusted for actual size */
+#define SDRAM_OR_PRELIM  (ORMASK(SDRAM_MAX_SIZE) | OR_CSNT_SAM | OR_G5LS)
+
+/* This is the Mode Select Register value for the SDRAM.
+ * Burst length: 4
+ * Burst Type: sequential
+ * CAS Latency: 2
+ * Write Burst Length: burst
+ */
+#define SDRAM_MODE   0x22      /* CAS latency 2, burst length 4 */
 
 /* ------------------------------------------------------------------------- */
 
-void _sdramdisable(void)
+long int initdram(int board_type)
 {
        volatile immap_t     *immap = (immap_t *)CFG_IMMR;
        volatile memctl8xx_t *memctl = &immap->im_memctl;
+       uint size_sdram = 0;
+       uint size_sdram9 = 0;
+       uint base = 0;          /* SDRAM must start at 0 */
+       int i;
 
-       memctl->memc_br4 = 0x00000000;
-
-       /* maybe we should turn off upmb here or something */
-}
+       upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
-/* ------------------------------------------------------------------------- */
-
-int initsdram(uint base, uint *noMbytes)
-{
-       uint m = 4;
-
-       /* This is needed only for the FADS board emulating the SIXNET board.
-        * The SXNI855T has no BCSRs.
+       /* Configure the refresh (mostly).  This needs to be
+        * based upon processor clock speed and optimized to provide
+        * the highest level of performance.
+        *
+        * Preliminary prescaler for refresh.
+        * This value is selected for four cycles in 31.2 us,
+        * which gives 8192 cycles in 64 milliseconds.
+        * This may be too fast, but works for any memory.
+        * It is adjusted to 4096 cycles in 64 milliseconds if
+        * possible once we know what memory we have.
+         *
+        * We have to be careful changing UPM registers after we
+        * ask it to run these commands.
+        *
+        * PTA - periodic timer period for our design is
+        *       50 MHz x 31.2us
+        *       ---------------  = 195
+        *       1 x 8 x 1
+        *
+        *    50MHz clock
+        *    31.2us refresh interval
+        *    SCCR[DFBRG] 0
+        *    PTP divide by 8
+        *    1 chip select
+         */
+       memctl->memc_mptpr = MPTPR_PTP_DIV8;    /* 0x0800 */
+       memctl->memc_mamr = SDRAM_MAMR_8COL & (~MAMR_PTAE); /* no refresh yet */
+
+       /* The SDRAM Mode Register value is shifted left 2 bits since
+        * A30 and A31 don't connect to the SDRAM for 32-bit wide memory.
         */
-       /* enable sdram,  _fads_sdraminit needs access to sdram */
-       *((uint *)BCSR1) |= BCSR1_SDRAM_EN;
-       *noMbytes = m;
-
-       if (!_initsdram(base, m)) {
-               return 0;
-       }
-       else {
-               *((uint *)BCSR1) &= ~BCSR1_SDRAM_EN; /* disable sdram */
-
-               _sdramdisable();
-
-               return -1;
-       }
-}
-
-long int initdram (int board_type)
-{
-       /* FADS: has 4MB SDRAM, put DRAM above it */
-       uint base = (unsigned long)0x00400000;
-       uint k, m, s;
-
-       k = (*((uint *)BCSR2) >> 23) & 0x0f;
-
-       m = 0;
-
-       switch(k & 0x3) {
-               /* "MCM36100 / MT8D132X" */
-               case 0x00 :
-                       m = 4;
-                       break;
-
-               /* "MCM36800 / MT16D832X" */
-               case 0x01 :
-                       m = 32;
-                       break;
-               /* "MCM36400 / MT8D432X" */
-               case 0x02 :
-                       m = 16;
-                       break;
-               /* "MCM36200 / MT16D832X ?" */
-               case 0x03 :
-                       m = 8;
-                       break;
-
-       }
-
-       switch(k >> 2) {
-               case 0x02 :
-                       k = 70;
-                       break;
-
-               case 0x03 :
-                       k = 60;
-                       break;
-
-               default :
-                       printf("unknown dramdelay (0x%x) - defaulting to 70 ns", k);
-                       k = 70;
-       }
-
-       /* the FADS is missing this bit, all rams treated as non-edo */
-       s = 0;
-
-       if(!_draminit(base, m, s, k)) {
-               uint    sdramsz;
-               *((uint *)BCSR1) &= ~BCSR1_DRAM_EN;  /* enable dram */
+       memctl->memc_mar = SDRAM_MODE << 2;     /* MRS code */
+       udelay(200);            /* SDRAM needs 200uS before set it up */
 
-               if (!initsdram(0x00000000, &sdramsz)) {
-                               m += sdramsz;
-                               printf("(%u MB SDRAM) ", sdramsz);
-               } else {
-                               _dramdisable();
+       /* Now run the precharge/nop/mrs commands. */
+       memctl->memc_mcr = SDRAM_MCR_PRE;
+       udelay(2);
 
-                               /********************************
-                               *DRAM ERROR, HALT PROCESSOR
-                               *********************************/
-                               while(1);
+       /* Run 8 refresh cycles (2 sets of 4) */
+       memctl->memc_mcr = SDRAM_MCR_REFR;      /* run refresh twice */
+       udelay(2);
 
-                               return -1;
-               }
+       /* some brands want Mode Register set after the refresh
+        * cycles. This shouldn't hurt anything for the brands
+        * that were happy with the first time we set it.
+        */
+       memctl->memc_mcr = SDRAM_MCR_MRS;
+       udelay(2);
 
-               return (m << 20);
-       }
-       else {
-               _dramdisable();
+       memctl->memc_mamr = SDRAM_MAMR_8COL;    /* enable refresh */
+       memctl->memc_or3 = SDRAM_OR_PRELIM;
+       memctl->memc_br3 = SDRAM_BR_VALUE + base;
 
-               /********************************
-               *DRAM ERROR, HALT PROCESSOR
-               *********************************/
-               while(1);
+       /* Some brands need at least 10 DRAM accesses to stabilize.
+        * It wont hurt the brands that don't.
+        */
+       for (i=0; i<10; ++i) {
+               volatile ulong *addr = (volatile ulong *)base;
+               ulong val;
 
-               return -1;
+               val = *(addr + i);
+               *(addr + i) = val;
        }
-}
 
-/* ------------------------------------------------------------------------- */
-
-#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-#error "SXNI855T has no PCMCIA port"
-#endif /* CFG_CMD_PCMCIA */
+       /* Check SDRAM memory Size in 8 column mode.
+        * For a 9 column memory we will get half the actual size.
+        */
+       size_sdram = ram_size((ulong *)0, SDRAM_MAX_SIZE);
 
-/* ------------------------------------------------------------------------- */
+       /* Check SDRAM memory Size in 9 column mode.
+        * For an 8 column memory we will see at most 4 megabytes.
+        */
+       memctl->memc_mamr = SDRAM_MAMR_9COL;
+       size_sdram9 = ram_size((ulong *)0, SDRAM_MAX_SIZE);
 
-/*
- * Miscellaneous platform dependent initializations while still
- * running in flash
- */
+       if (size_sdram < size_sdram9)   /* leave configuration at 9 columns */
+               size_sdram = size_sdram9;
+       else                            /* go back to 8 columns */
+               memctl->memc_mamr = SDRAM_MAMR_8COL;
 
-int
-misc_init_f(void)
-{
-       /* configure the board features, such rs232 and ethernet */
-       /* These are needed only for the FADS board emulating the SIXNET board.
-        * The SXNI855T has no BCSRs.
+       /* adjust or3 for actual size of SDRAM
         */
-       *((uint *) BCSR1) &= ~CFG_BCSR1_CLEAR;
-       *((uint *) BCSR1) |= CFG_BCSR1_SET;
-       *((uint *) BCSR4) &= ~CFG_BCSR4_CLEAR;
-       *((uint *) BCSR4) |= CFG_BCSR4_SET;
-
-#if defined(CONFIG_FEC_ENET)
-       /* configure FADS for fast (FEC) ethernet, half-duplex */
-       /* The LXT970 needs about 50ms to recover from reset, so
-        * wait for it by discovering the PHY before leaving eth_init().
+       memctl->memc_or3 |= ORMASK(size_sdram);
+
+       /* Adjust refresh rate depending on SDRAM type.
+        * For types > 128 MBit (32 Mbyte for 2 x16 devices) leave
+        * it at the current (fast) rate.
+        * For 16, 64 and 128 MBit half the rate will do.
         */
-       {
-               volatile uint *bcsr4 = (volatile uint *) BCSR4;
-               *bcsr4 = (*bcsr4 & ~(BCSR4_FETH_EN | BCSR4_FETHCFG1))
-                       | (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST);
-
-               /* reset the LXT970 PHY */
-               *bcsr4 &= ~BCSR4_FETHRST;
-               udelay (10);
-               *bcsr4 |= BCSR4_FETHRST;
-               udelay (10);
-       }
-#endif
+       if (size_sdram <= 32 * 1024 * 1024)
+               memctl->memc_mptpr = MPTPR_PTP_DIV16;   /* 0x0400 */
 
-    return 0;  /* success */
+       return (size_sdram);
 }
+

diff --git a/board/sixnet/sixnet.h b/board/sixnet/sixnet.h
index 0bd8e84035562bf60568832775c12f96a5222c61..e631874972efcef0d430d0424ede10b0149ab8a1 100644 (file)
--- a/board/sixnet/sixnet.h
+++ b/board/sixnet/sixnet.h
@@ -21,24 +21,16 @@
  * MA 02111-1307 USA
  */
 
-/****************************************************************************
- * FLASH Memory Map as used by FADS Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0xFE00_0000     Start of Flash -----------------
- * | MON8xx code           | 0xFE00_0100     Reset Vector
- * +-----------------------+ 0xFE0?_????
- * | (unused)              |
- * +-----------------------+ 0xFE01_FF00
- * | Ethernet Addresses    |                 0x78
- * +-----------------------+ 0xFE01_FF78
- * | (Reserved for MON8xx) |                 0x44
- * +-----------------------+ 0xFE01_FFBC
- * | Lock Address          |                 0x04
- * +-----------------------+ 0xFE01_FFC0                     ^
- * | Hardware Information  |                 0x40            | MON8xx
- * +=======================+ 0xFE02_0000 (sector border)    -----------------
- * | Autostart Header      |                                 | Applications
- * | ...                   |                                 v
+/*
+ * Memory map:
  *
- *****************************************************************************/
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
+ */

diff --git a/common/board.c b/common/board.c
index 6414a3ddfae0d3e2f962fabed32c7c0e0f7b7efc..7f515463c365e84b7bda3ce973fa61e5a5510032 100644 (file)
--- a/common/board.c
+++ b/common/board.c
@@ -223,7 +223,7 @@ board_init_f (ulong bootflag)
     dpram_init ();
 #endif
 
-#if defined(CONFIG_HYMOD)
+#if defined(CONFIG_HYMOD) || defined(CONFIG_BOARD_POSTCLK_INIT)
     /*
      * This initialisation is for very early stuff that requires the i2c
      * driver (which needs to know the clocks, to calculate the dividers,
@@ -285,8 +285,9 @@ board_init_f (ulong bootflag)
 #endif /* CONFIG_HW_WATCHDOG */
     WATCHDOG_RESET();
 
-#if defined(CONFIG_COGENT) || defined(CONFIG_SXNI855T) || \
-    defined(CONFIG_RSD_PROTO) || defined(CONFIG_HYMOD) || \
+#if defined(CONFIG_COGENT)     || \
+    defined(CONFIG_HYMOD)      || \
+    defined(CONFIG_RSD_PROTO)  || \
     defined(CONFIG_W7O)
     /* miscellaneous platform dependent initialisations */
     if (misc_init_f() < 0) {

diff --git a/common/cmd_pcmcia.c b/common/cmd_pcmcia.c
index 7e5b5c1d462e1b0eb570f3331dbc550a1cfe6ae6..b47772750618f0681a491f97a1f8cc48242a192b 100644 (file)
--- a/common/cmd_pcmcia.c
+++ b/common/cmd_pcmcia.c
@@ -69,7 +69,7 @@
 int pcmcia_on (void);
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
-static void pcmcia_off (void);
+static int  pcmcia_off (void);
 static int  hardware_disable(int slot);
 #endif
 static int  hardware_enable (int slot);
@@ -225,7 +225,7 @@ int pcmcia_on (void)
 
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
 
-static void pcmcia_off (void)
+static int pcmcia_off (void)
 {
        int i;
        pcmcia_win_t *win;

diff --git a/cpu/mpc8xx/cpu_init.c b/cpu/mpc8xx/cpu_init.c
index ba4e8a8d5f2bbacc3c4929a66aa643728ff0fd82..9caee677caa85c0c21f38eec5c7af8b0598e039c 100644 (file)
--- a/cpu/mpc8xx/cpu_init.c
+++ b/cpu/mpc8xx/cpu_init.c
@@ -143,7 +143,6 @@ cpu_init_f (volatile immap_t *immr)
     defined(CONFIG_RPXCLASSIC) || \
     defined(CONFIG_RPXLITE)    || \
     defined(CONFIG_SPD823TS)   || \
-    defined(CONFIG_SXNI855T)   || \
    (defined(CONFIG_MPC860T) && defined(CONFIG_FADS))
 
     memctl->memc_br0 = CFG_BR0_PRELIM; /* XXX ??? XXX ??? XXX */

diff --git a/include/config_EVB64260.h b/include/config_EVB64260.h
index e2e8f5c97d2f42f8db45f432aae720fedd248fcc..e5179abae6ee8389dbcd25ac690f3d2a598b605d 100644 (file)
--- a/include/config_EVB64260.h
+++ b/include/config_EVB64260.h
@@ -123,7 +123,7 @@
 #define CFG_MEMTEST_START      0x00400000      /* memtest works on     */
 #define CFG_MEMTEST_END                0x00C00000      /* 4 ... 12 MB in DRAM  */
 
-#define        CFG_LOAD_ADDR           0x300000        /* default load address */
+#define        CFG_LOAD_ADDR           0x00300000      /* default load address */
 
 #define        CFG_HZ                  1000            /* decr freq: 1ms ticks */
 #define CFG_BUS_HZ             100000000       /* 100 MHz              */
@@ -155,9 +155,9 @@
 #define        CFG_SDRAM_BASE          0x00000000
 #define CFG_FLASH_BASE         0xfff00000
 #define CFG_RESET_ADDRESS      0xfff00100
-#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 128 kB for Monitor */
+#define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
-#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc */
+#define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 256 kB for malloc */
 
 /* areas to map different things with the GT in physical space */
 #define CFG_DRAM_BANKS         4
@@ -191,33 +191,49 @@
         /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100      */
         /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4       */
 
+#if 0 /* Wrong?? NTL */
 #define CFG_MPP_CONTROL_0      0x53541717      /* InitAct EOT[4] DBurst TCEn[1] */
                                                /* DMAAck[1:0] GNT0[1:0] */
+#else
+#define CFG_MPP_CONTROL_0      0x53547777      /* InitAct EOT[4] DBurst TCEn[1] */
+                                               /* REQ0[1:0] GNT0[1:0] */
+#endif
 #define CFG_MPP_CONTROL_1      0x44009911      /* TCEn[4] TCTcnt[4] GPP[13:12] */
                                                /* DMAReq[4] DMAAck[4] WDNMI WDE */
+#if 0 /* Wrong?? NTL */
 #define CFG_MPP_CONTROL_2      0x40091818      /* TCTcnt[0] GPP[22:21] BClkIn */
                                                /* DMAAck[1:0] GNT1[1:0] */
+#else
+#define CFG_MPP_CONTROL_2      0x40098888      /* TCTcnt[0] */
+                                               /* GPP[22] (RS232IntB or PCI1Int) */
+                                               /* GPP[21] (RS323IntA) */
+                                               /* BClkIn */
+                                               /* REQ1[1:0] GNT1[1:0] */
+#endif
 
 #if 0 /* Wrong?? NTL */
 # define CFG_MPP_CONTROL_3     0x00090066      /* GPP[31:29] BClkOut0 */
                                                /* GPP[27:26] Int[1:0] */
 #else
-# define CFG_MPP_CONTROL_3     0x00090000      /* GPP[31:29] BClkOut0 */
-                                                /* GPP[27:26]  */
-                                                /* GPP[25:24] (pci int[1:0]) */
+# define CFG_MPP_CONTROL_3     0x22090066      /* MREQ MGNT */
+                                                /* GPP[29]    (PCI1Int) */
+                                                /* BClkOut0 */
+                                                /* GPP[27]    (PCI0Int) */
+                                                /* GPP[26]    (RtcInt or PCI1Int) */
+                                                /* CPUInt[25:24] */
 #endif
 
-# define CFG_SERIAL_PORT_MUX   0x00000102 /* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
+# define CFG_SERIAL_PORT_MUX   0x00000102      /* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
 
 #if 0 /* Wrong?? - NTL */
 # define CFG_GPP_LEVEL_CONTROL 0x000002c6
 #else 
-# define CFG_GPP_LEVEL_CONTROL 0xc3400000      /* 0110 0011 0100 0000 */
-                                                /* gpp[30]:gpp[29] */
-                                                /* gpp[25:24] (pci int[1:0]) */
-                                                /* gpp[22] */
+# define CFG_GPP_LEVEL_CONTROL 0x2c600000      /* 0010 1100 0110 0000 */
+                                                /* gpp[29] */
+                                               /* gpp[27:26] */
+                                                /* gpp[22:21] */
 
-# define CFG_SDRAM_CONFIG      0xd8e10200      /* 0x448 */
+# define CFG_SDRAM_CONFIG      0xd8e18200      /* 0x448 */
                                /* idmas use buffer 1,1
                                   comm use buffer 0
                                   pci use buffer 1,1
@@ -228,10 +244,10 @@
                                /* 31:26  25 23  20 19 18 16 */
                                /* 110110 00 111 0  0  00 1 */
                                /* refresh_count=0x200
-                                  phisical interleaving enable
+                                  phisical interleaving disable
                                   virtual interleaving enable */
                                /* 15 14 13:0 */
-                               /* 0  0  0x200 */
+                               /* 1  0  0x200 */
 #endif
 
 #define CFG_DUART_IO           CFG_DEV2_SPACE
@@ -333,6 +349,7 @@
 
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI          1
 
 #define        CFG_ENV_IS_IN_FLASH     1
 #define        CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */

diff --git a/include/config_SXNI855T.h b/include/config_SXNI855T.h
index 83eaa73dcdedc125fd3bd6013f483001085a168a..ee104d5279bf6f77d9cdaffe3af4fc3904961f50 100644 (file)
--- a/include/config_SXNI855T.h
+++ b/include/config_SXNI855T.h
@@ -1,11 +1,10 @@
 /*
  * PPCBoot configuration for SIXNET SXNI855T CPU board.
- * This board is based on the Motorola FADS board, so this
- * file is based on config_FADS860T.h, see it for additional
+ * This board is based (loosely) on the Motorola FADS board, so this
+ * file is based (loosely) on config_FADS860T.h, see it for additional
  * credits.
  *
- * (C) Copyright 2000
- * Dave Ellis, SIXNET, dge@sixnetio.com
+ * Copyright (c) 2000-2002 Dave Ellis, SIXNET, dge@sixnetio.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -25,16 +24,20 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  *
- * This configuration is still in preliminary design, so far it
- * works only with a FADS 860T emulating the final design.
  */
 
 /*
- * ### FIXME - these are still from config_FADS860T.h
- * ff010000 -> ff01ffff : BCSR       connected to CS1, setup by 8xxrom
- * ff000000 -> ff00ffff : IMAP       internal in the cpu
- * fe000000 -> ffnnnnnn : flash      connected to CS0, setup by 8xxrom
- * 00000000 -> nnnnnnnn : sdram/dram setup by 8xxrom
+ * Memory map:
+ *
+ *   ff100000 -> ff13ffff : FPGA        CS1
+ *   ff030000 -> ff03ffff : EXPANSION   CS7
+ *   ff020000 -> ff02ffff : DATA FLASH  CS4
+ *   ff018000 -> ff01ffff : UART B      CS6/UPMB
+ *   ff010000 -> ff017fff : UART A      CS5/UPMB
+ *   ff000000 -> ff00ffff : IMAP                   internal to the MPC855T
+ *   f8000000 -> fbffffff : FLASH       CS0        up to 64MB
+ *   f4000000 -> f7ffffff : NVSRAM      CS2        up to 64MB
+ *   00000000 -> 0fffffff : SDRAM       CS3/UPMA   up to 256MB
  */
 
 /* ------------------------------------------------------------------------- */
@@ -63,6 +66,7 @@
 
 #define        CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
 #undef CONFIG_8xx_CONS_SMC2
+#undef CONFIG_8xx_CONS_SCC1
 #undef CONFIG_8xx_CONS_NONE
 #define CONFIG_BAUDRATE                9600
 #define CONFIG_LOADS_ECHO      1       /* echo on for serial download  */
@@ -77,11 +81,16 @@
 #define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds     */
 #endif
 
-#define CONFIG_BOOTCOMMAND     "bootm 02880000 02900000" /* autoboot command */
-#define CONFIG_BOOTARGS                "root=/dev/ram ip=10.1.0.147:::255.128.0.0:fads::off"
+#define CONFIG_BOOTCOMMAND     "bootm f8040000 f8100000" /* autoboot command */
+#define CONFIG_BOOTARGS                "root=/dev/ram ip=off"
+
+#define CONFIG_MISC_INIT_R             /* have misc_init_r() function */
+#define CONFIG_BOARD_POSTCLK_INIT      /* have board_postclk_init() function */
 
 #undef CONFIG_WATCHDOG                 /* watchdog disabled            */
 
+#define        CONFIG_RTC_DS1306               /* Dallas 1306 real time clock  */
+
 #define        CONFIG_SOFT_I2C                 /* Software I2C support enabled */
 # define CFG_I2C_SPEED         50000
 # define CFG_I2C_SLAVE         0xFE
@@ -91,13 +100,10 @@
                                        /* 5 bits of the address        */
 
 #define        CONFIG_FEC_ENET         1       /* use FEC ethernet  */
-#undef CONFIG_SCC1_ENET                /* disable SCC1 ethernet */
-#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
-#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
-#endif
+
 #define CFG_DISCOVER_PHY
 
-#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
+#define CONFIG_COMMANDS                (CONFIG_CMD_DFL | CFG_CMD_EEPROM | CFG_CMD_DATE)
 
 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 #include <cmd_confdefs.h>
@@ -133,7 +139,7 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR                       0xFF000000
+#define CFG_IMMR               0xFF000000
 #define CFG_IMMR_SIZE          ((uint)(64 * 1024))
 
 /*-----------------------------------------------------------------------
@@ -151,11 +157,19 @@
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define        CFG_SDRAM_BASE          0x00000000
+#define        CFG_SRAM_BASE           0xF4000000
+#define        CFG_SRAM_SIZE           0x04000000      /* autosize up to 64Mbyte */
 
-#define CFG_FLASH_BASE         0x02800000
-
+#define CFG_FLASH_BASE         0xF8000000
 #define CFG_FLASH_SIZE         ((uint)(8 * 1024 * 1024))       /* max 8Mbyte */
 
+#define CFG_DFLASH_BASE                0xff020000 /* DiskOnChip or NAND FLASH */
+#define CFG_DFLASH_SIZE                0x00010000
+
+#define CFG_FPGA_BASE          0xFF100000      /* Xilinx FPGA */
+#define CFG_FPGA_PROG          0xFF130000      /* Programming address */
+#define CFG_FPGA_SIZE          0x00040000      /* 256KiB usable */
+
 #define        CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 #define CFG_MONITOR_BASE       CFG_FLASH_BASE
 #define        CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
@@ -170,10 +184,13 @@
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
-#define CFG_MAX_FLASH_SECT     8       /* max number of sectors on one chip    */
+/* Intel 28F640 has 135, 127 64K sectors in 8MB, + 8 more for 8K boot blocks.
+ * AMD 29LV641 has 128 64K sectors in 8MB
+ */
+#define CFG_MAX_FLASH_SECT     135     /* max number of sectors on one chip    */
 
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms)      */
-#define CFG_FLASH_WRITE_TOUT   500             /* Timeout for Flash Write (in ms)      */
+#define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms)      */
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
@@ -242,185 +259,75 @@
 #define CFG_DER                0
 
 /* Because of the way the 860 starts up and assigns CS0 the
-* entire address space, we have to set the memory controller
-* differently.  Normally, you write the option register
-* first, and then enable the chip select by writing the
-* base register.  For CS0, you must write the base register
-* first, followed by the option register.
-*/
+ * entire address space, we have to set the memory controller
+ * differently.  Normally, you write the option register
+ * first, and then enable the chip select by writing the
+ * base register.  For CS0, you must write the base register
+ * first, followed by the option register.
+ */
 
 /*
  * Init Memory Controller:
  *
- * BR0/1 and OR0/1 (FLASH)
+ **********************************************************
+ * BR0 and OR0 (FLASH)
  */
-/* the other CS:s are determined by looking at parameters in BCSRx */
-
-#define BCSR_ADDR              ((uint) 0xFF010000)
-#define BCSR_SIZE              ((uint)(64 * 1024))
-
-#define FLASH_BASE0_PRELIM     0x02800000      /* FLASH bank #0        */
-#define FLASH_BASE1_PRELIM     0x00000000      /* FLASH bank #1 not used */
 
-#define CFG_REMAP_OR_AM                0x80000000      /* OR addr mask */
-#define CFG_PRELIM_OR_AM       0xFFE00000      /* OR addr mask */
+#define CFG_PRELIM_OR0_AM      0xFC000000      /* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0       */
 #define CFG_OR_TIMING_FLASH    (OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_REMAP  (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM (CFG_PRELIM_OR0_AM | CFG_OR_TIMING_FLASH)
 
-#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
-#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+#define CONFIG_FLASH_16BIT
+#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
+#define CFG_FLASH_PROTECTION   /* need to lock/unlock sectors in hardware */
 
-/* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_REMAP  CFG_OR0_REMAP
-#define CFG_OR1_PRELIM 0xffff8110              /* 64Kbyte address space */
-#define CFG_BR1_PRELIM ((BCSR_ADDR) | BR_V )
-
-
-/*
- * Memory Periodic Timer Prescaler
+/**********************************************************
+ * BR1 and OR1 (FPGA)
+ * These preliminary values are also the final values.
  */
+#define CFG_OR_TIMING_FPGA \
+       (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+#define CFG_BR1_PRELIM ((CFG_FPGA_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR1_PRELIM (((-CFG_FPGA_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_FPGA)
+
+/**********************************************************
+ * BR4 and OR4 (data flash)
+ * These preliminary values are also the final values.
+ */
+#define CFG_OR_TIMING_DFLASH \
+       (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
+#define CFG_BR4_PRELIM ((CFG_DFLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
+#define CFG_OR4_PRELIM (((-CFG_DFLASH_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_DFLASH)
 
-/* periodic timer for refresh */
-#define CFG_MAMR_PTA           97      /* start with divider for 100 MHz       */
-
-/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit    */
-#define CFG_MPTPR_2BK_4K       MPTPR_PTP_DIV16         /* setting for 2 banks  */
-#define CFG_MPTPR_1BK_4K       MPTPR_PTP_DIV32         /* setting for 1 bank   */
-
-/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit                */
-#define CFG_MPTPR_2BK_8K       MPTPR_PTP_DIV8          /* setting for 2 banks  */
-#define CFG_MPTPR_1BK_8K       MPTPR_PTP_DIV16         /* setting for 1 bank   */
-
-/*
- * MAMR settings for SDRAM
+/**********************************************************
+ * BR5/6 and OR5/6 (Dual UART)
  */
+#define CFG_DUART_SIZE 0x8000  /* 32K window, only uses 8 bytes */
+#define CFG_DUARTA_BASE        0xff010000
+#define CFG_DUARTB_BASE        0xff018000
 
-/* 8 column SDRAM */
-#define CFG_MAMR_8COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
-                        MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
-/* 9 column SDRAM */
-#define CFG_MAMR_9COL  ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
-                        MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
-                        MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
+#define DUART_MBMR     0
+#define DUART_OR_VALUE (ORMASK(CFG_DUART_SIZE) | OR_G5LS| OR_BI)
+#define DUART_BR_VALUE (BR_MS_UPMB | BR_PS_8 | BR_V)
+#define DUART_BR5_VALUE ((CFG_DUARTA_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
+#define DUART_BR6_VALUE ((CFG_DUARTB_BASE & BR_BA_MSK ) | DUART_BR_VALUE)
 
-#define CFG_MAMR               0x13a01114
-/*
- * Internal Definitions
+/**********************************************************
  *
  * Boot Flags
  */
 #define        BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 #define BOOTFLAG_WARM  0x02            /* Software reboot                      */
 
-
-/* values according to the manual */
-
-#define        BCSR0                   ((uint) (BCSR_ADDR + 00))
-#define        BCSR1                   ((uint) (BCSR_ADDR + 0x04))
-#define        BCSR2                   ((uint) (BCSR_ADDR + 0x08))
-#define        BCSR3                   ((uint) (BCSR_ADDR + 0x0c))
-#define        BCSR4                   ((uint) (BCSR_ADDR + 0x10))
-
-/* FADS bitvalues by Helmut Buchsbaum
- * see MPC8xxADS User's Manual for a proper description
- * of the following structures
- */
-
-#define BCSR0_ERB       ((uint)0x80000000)
-#define BCSR0_IP        ((uint)0x40000000)
-#define BCSR0_BDIS      ((uint)0x10000000)
-#define BCSR0_BPS_MASK  ((uint)0x0C000000)
-#define BCSR0_ISB_MASK  ((uint)0x01800000)
-#define BCSR0_DBGC_MASK ((uint)0x00600000)
-#define BCSR0_DBPC_MASK ((uint)0x00180000)
-#define BCSR0_EBDF_MASK ((uint)0x00060000)
-
-#define BCSR1_FLASH_EN           ((uint)0x80000000)
-#define BCSR1_DRAM_EN            ((uint)0x40000000)
-#define BCSR1_ETHEN              ((uint)0x20000000)
-#define BCSR1_IRDEN              ((uint)0x10000000)
-#define BCSR1_FLASH_CFG_EN       ((uint)0x08000000)
-#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
-#define BCSR1_BCSR_EN            ((uint)0x02000000)
-#define BCSR1_RS232EN_1          ((uint)0x01000000)
-#define BCSR1_PCCEN              ((uint)0x00800000)
-#define BCSR1_PCCVCC0            ((uint)0x00400000)
-#define BCSR1_PCCVPP_MASK        ((uint)0x00300000)
-#define BCSR1_DRAM_HALF_WORD     ((uint)0x00080000)
-#define BCSR1_RS232EN_2          ((uint)0x00040000)
-#define BCSR1_SDRAM_EN           ((uint)0x00020000)
-#define BCSR1_PCCVCC1            ((uint)0x00010000)
-
-#define BCSR2_FLASH_PD_MASK      ((uint)0xF0000000)
-#define BCSR2_DRAM_PD_MASK       ((uint)0x07800000)
-#define BCSR2_DRAM_PD_SHIFT      (23)
-#define BCSR2_EXTTOLI_MASK       ((uint)0x00780000)
-#define BCSR2_DBREVNR_MASK       ((uint)0x00030000)
-
-#define BCSR3_DBID_MASK          ((ushort)0x3800)
-#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
-#define BCSR3_BREVNR0            ((ushort)0x0080)
-#define BCSR3_FLASH_PD_MASK      ((ushort)0x0070)
-#define BCSR3_BREVN1             ((ushort)0x0008)
-#define BCSR3_BREVN2_MASK        ((ushort)0x0003)
-
-#define BCSR4_ETHLOOP            ((uint)0x80000000)
-#define BCSR4_TFPLDL             ((uint)0x40000000)
-#define BCSR4_TPSQEL             ((uint)0x20000000)
-#define BCSR4_SIGNAL_LAMP        ((uint)0x10000000)
-
-#ifdef CONFIG_MPC860T
-#define BCSR4_FETH_EN            ((uint)0x08000000)
-#define BCSR4_FETHCFG0           ((uint)0x04000000)
-#define BCSR4_FETHFDE            ((uint)0x02000000)
-#define BCSR4_FETHCFG1           ((uint)0x00400000)
-#define BCSR4_FETHRST            ((uint)0x00200000)
-#endif /* CONFIG_MPC860T */
-
-#define CONFIG_DRAM_50MHZ              1
-#define CONFIG_SDRAM_50MHZ
-
-#ifdef CONFIG_MPC860T
-
-/* Interrupt level assignments.
-*/
-#define FEC_INTERRUPT  SIU_LEVEL1      /* FEC interrupt */
-
-#endif /* CONFIG_MPC860T */
-
-/* We don't use the 8259.
-*/
-#define NR_8259_INTS   0
-
-/* Machine type
-*/
-#define _MACH_8xx (_MACH_fads)
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#define CFG_BCSR1_SET  0       /* no bits to set to 1 */
-/* NOTE - These are low to enable (but we use the names in the FADS manual) */
-#ifdef CFG_SCC1_ENET
-#define CFG_BCSR1_CLEAR (BCSR1_RS232EN_1 | BCSR1_RS232EN_2 | BCSR1_ETHEN)
-#else
-#define CFG_BCSR1_CLEAR (BCSR1_RS232EN_1 | BCSR1_RS232EN_2)
-#endif
-
-#if defined(CONFIG_FEC_ENET)
-#define CFG_BCSR4_SET  (BCSR4_FETHCFG0 | BCSR4_FETHFDE | BCSR4_FETHRST)
-#define CFG_BCSR4_CLEAR        (BCSR4_FETH_EN | BCSR4_FETHCFG1)
-#endif
-
 #define CONFIG_RESET_ON_PANIC          /* reset if system panic() */
 
 /* to put environment in EEROM */
 #define        CFG_ENV_IS_IN_EEPROM    1
 #define CFG_ENV_OFFSET         0       /* Start right at beginning of NVRAM */
-#define CFG_ENV_SIZE           512     /* Use only a part of it*/
+#define CFG_ENV_SIZE           1024    /* Use only a part of it*/
 #define CONFIG_I2C_X           1       /* EEPROM uses 16-bit address */
 
 #if 1

diff --git a/include/config_ZUMA.h b/include/config_ZUMA.h
index ca5a8501dfae84674b3a0fa1f7bdb2bbf64e9255..8cd6cf2f56531a0cc7afac097f995e356043af56 100644 (file)
--- a/include/config_ZUMA.h
+++ b/include/config_ZUMA.h
@@ -310,6 +310,7 @@
 
 #define CFG_FLASH_ERASE_TOUT   120000  /* Timeout for Flash Erase (in ms) */
 #define CFG_FLASH_WRITE_TOUT   500     /* Timeout for Flash Write (in ms) */
+#define CFG_FLASH_CFI          1
 
 #define CFG_ENV_IS_IN_FLASH    1
 #define CFG_ENV_SIZE           0x1000  /* Total Size of Environment Sector */

diff --git a/include/config_lwmon.h b/include/config_lwmon.h
index a6e265a502f813e4b828aed0b199001e240e1e6a..6b8b511386bf906a2203b91df85adb7bf7e88723 100644 (file)
--- a/include/config_lwmon.h
+++ b/include/config_lwmon.h
@@ -448,9 +448,9 @@
 #define TOUCHPNL_OR_AM         0xFFFF8000
 #define TOUCHPNL_TIMING                OR_SCY_0_CLK
 
-#define CFG_OR5 (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
-                TOUCHPNL_TIMING )
-#define CFG_BR5 ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
+#define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
+                        TOUCHPNL_TIMING )
+#define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 
 /*
  * Memory Periodic Timer Prescaler

diff --git a/include/config_ppmc8260.h b/include/config_ppmc8260.h
new file mode 100644 (file)
index 0000000..456e055
--- /dev/null
+++ b/include/config_ppmc8260.h
@@ -0,0 +1,1004 @@
+/*
+ * (C) Copyright 2000
+ * Murray Jensen <Murray.Jensen@cmst.csiro.au>
+ *
+ * (C) Copyright 2000
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2001
+ * Advent Networks, Inc. <http://www.adventnetworks.com>
+ * Jay Monkman <jtm@smoothsmoothie.com>
+ *
+ * Configuation settings for the WindRiver PPMC8260 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*****************************************************************************
+ *
+ * These settings must match the way _your_ board is set up
+ *
+ *****************************************************************************/
+
+/* What is the oscillator's (UX2) frequency in Hz? */
+#define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
+
+/*-----------------------------------------------------------------------
+ * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
+ *-----------------------------------------------------------------------
+ * What should MODCK_H be? It is dependent on the oscillator
+ * frequency, MODCK[1-3], and desired CPM and core frequencies.
+ * Here are some example values (all frequencies are in MHz):
+ *
+ * MODCK_H   MODCK[1-3]         Osc    CPM    Core  S2-6   S2-7   S2-8
+ * -------   ----------         ---    ---    ----  -----  -----  -----
+ * 0x2      0x2         33     133    133   Close  Open   Close
+ * 0x2      0x3         33     133    166   Close  Open   Open
+ * 0x2      0x4         33     133    200   Open   Close  Close
+ * 0x2      0x5         33     133    233   Open   Close  Open
+ * 0x2      0x6         33     133    266   Open   Open   Close
+ *
+ * 0x5      0x5         66     133    133   Open   Close  Open
+ * 0x5      0x6         66     133    166   Open   Open   Close
+ * 0x5      0x7         66     133    200   Open   Open   Open
+ * 0x6      0x0         66     133    233   Close  Close  Close
+ * 0x6      0x1         66     133    266   Close  Close  Open
+ * 0x6      0x2         66     133    300   Close  Open   Close
+ */
+#define CFG_PPMC_MODCK_H 0x05
+
+/* Define this if you want to boot from 0x00000100. If you don't define
+ * this, you will need to program the bootloader to 0xfff00000, and
+ * get the hardware reset config words at 0xfe000000. The simplest
+ * way to do that is to program the bootloader at both addresses.
+ * It is suggested that you just let PPCBOOT live at 0x00000000.
+ */
+#define CFG_PPMC_BOOT_LOW 1
+
+/* What should the base address of the main FLASH be and how big is
+ * it (in MBytes)? This must contain TEXT_BASE from board/ppmc8260/config.mk
+ * The main FLASH is whichever is connected to *CS0. PPCBOOT expects
+ * this to be the SIMM.
+ */
+#define CFG_FLASH0_BASE 0xFE000000
+#define CFG_FLASH0_SIZE 16
+
+/* What should be the base address of the first SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM0_BASE 0x00000000
+#define CFG_SDRAM0_SIZE 128
+
+/* What should be the base address of the second SDRAM DIMM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM1_BASE 0x08000000
+#define CFG_SDRAM1_SIZE 128
+
+/* What should be the base address of the on board SDRAM and how big is
+ * it (in Mbytes)?
+*/
+#define CFG_SDRAM2_BASE 0x38000000
+#define CFG_SDRAM2_SIZE 16
+
+/* What should be the base address of the MAILBOX  and how big is it
+ * (in Bytes)
+ * The eeprom lives at CFG_MAILBOX_BASE + 0x80000000
+ */
+#define CFG_MAILBOX_BASE 0x32000000
+#define CFG_MAILBOX_SIZE 8192
+
+/* What is the base address of the I/O select lines and how big is it
+ * (In Mbytes)?
+ */
+
+#define CFG_IOSELECT_BASE 0xE0000000
+#define CFG_IOSELECT_SIZE 32
+
+
+/* What should be the base address of the LEDs and switch S0?
+ * If you don't want them enabled, don't define this.
+ */
+#define CFG_LED_BASE 0xF1000000
+
+/*
+ * PPMC8260 with 256 16 MB DIMM:
+ *
+ *     0x0000 0000     Exception Vector code, 8k
+ *          :
+ *     0x0000 1FFF
+ *     0x0000 2000     Free for Application Use
+ *          :
+ *          :
+ *
+ *          :
+ *          :
+ *     0x0FF5 FF30     Monitor Stack (Growing downward)
+ *                    Monitor Stack Buffer (0x80)
+ *     0x0FF5 FFB0     Board Info Data
+ *     0x0FF6 0000     Malloc Arena
+ *          :              CFG_ENV_SECT_SIZE, 256k
+ *          :              CFG_MALLOC_LEN,    128k
+ *     0x0FFC 0000     RAM Copy of Monitor Code
+ *          :              CFG_MONITOR_LEN,   256k
+ *     0x0FFF FFFF     [End of RAM], CFG_SDRAM_SIZE - 1
+ */
+
+
+/*
+ * select serial console configuration
+ *
+ * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
+ * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
+ * for SCC).
+ *
+ * if CONFIG_CONS_NONE is defined, then the serial console routines must
+ * defined elsewhere.
+ * The console can be on SMC1 or SMC2
+ */
+#define CONFIG_CONS_ON_SMC     1       /* define if console on SMC */
+#undef CONFIG_CONS_ON_SCC              /* define if console on SCC */
+#undef CONFIG_CONS_NONE                /* define if console on neither */
+#define CONFIG_CONS_INDEX      1       /* which SMC/SCC channel for console */
+
+/*
+ * select ethernet configuration
+ *
+ * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
+ * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
+ * for FCC)
+ *
+ * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
+ * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
+ * from CONFIG_COMMANDS to remove support for networking.
+ */
+
+#undef CONFIG_ETHER_ON_SCC             /* define if ethernet on SCC    */
+#define CONFIG_ETHER_ON_FCC            /* define if ethernet on FCC    */
+#undef CONFIG_ETHER_NONE               /* define if ethernet on neither */
+#define CONFIG_ETHER_INDEX     2       /* which SCC/FCC channel for ethernet */
+#define CONFIG_MII                     /* MII PHY management   */
+#define CONFIG_BITBANGMII              /* bit-bang MII PHY management  */
+/*
+ * Port pins used for bit-banged MII communictions (if applicable).
+ */
+#define MDIO_PORT      2       /* Port C */
+#define MDIO_ACTIVE    (iop->pdir |=  0x00400000)
+#define MDIO_TRISTATE  (iop->pdir &= ~0x00400000)
+#define MDIO_READ      ((iop->pdat &  0x00400000) != 0)
+
+#define MDIO(bit)      if(bit) iop->pdat |=  0x00400000; \
+                       else    iop->pdat &= ~0x00400000
+
+#define MDC(bit)       if(bit) iop->pdat |=  0x00200000; \
+                       else    iop->pdat &= ~0x00200000
+
+#define MIIDELAY       udelay(1)
+
+
+/* Define this to reserve an entire FLASH sector (256 KB) for
+ * environment variables. Otherwise, the environment will be
+ * put in the same sector as ppcboot, and changing variables
+ * will erase ppcboot temporarily
+ */
+#define CFG_ENV_IN_OWN_SECT    1
+
+/* Define to allow the user to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+/* What should the console's baud rate be? */
+#define CONFIG_BAUDRATE                9600
+
+/* Ethernet MAC address */
+
+#define CONFIG_ETHADDR         00:a0:1e:90:2b:00
+
+/* Define this to set the last octet of the ethernet address
+ * from the DS0-DS7 switch and light the leds with the result
+ * The DS0-DS7 switch and the leds are backwards with respect
+ * to each other. DS7 is on the board edge side of both the
+ * led strip and the DS0-DS7 switch.
+ */
+#define CONFIG_MISC_INIT_R
+
+/* Set to a positive value to delay for running BOOTCOMMAND */
+#define CONFIG_BOOTDELAY       5       /* autoboot after 5 seconds */
+
+#if 0
+/* Be selective on what keys can delay or stop the autoboot process
+ *     To stop use: " "
+ */
+# define CONFIG_AUTOBOOT_KEYED
+# define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, press \" \" to stop\n"
+# define CONFIG_AUTOBOOT_STOP_STR      " "
+# undef CONFIG_AUTOBOOT_DELAY_STR
+# define DEBUG_BOOTKEYS                0
+#endif
+
+/* Define a command string that is automatically executed when no character
+ * is read on the console interface withing "Boot Delay" after reset.
+ */
+#define CONFIG_BOOT_ROOT_INITRD 0      /* Use ram disk for the root file system */
+#define CONFIG_BOOT_ROOT_NFS   1       /* Use a NFS mounted root file system */
+
+#if CONFIG_BOOT_ROOT_INITRD
+#define CONFIG_BOOTCOMMAND \
+       "version;" \
+       "echo;" \
+       "bootp;" \
+       "setenv bootargs root=/dev/ram0 rw " \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+       "bootm"
+#endif /* CONFIG_BOOT_ROOT_INITRD */
+
+#if CONFIG_BOOT_ROOT_NFS
+#define CONFIG_BOOTCOMMAND \
+       "version;" \
+       "echo;" \
+       "bootp;" \
+       "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
+       "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
+       "bootm"
+#endif /* CONFIG_BOOT_ROOT_NFS */
+
+/* Add support for a few extra bootp options like:
+ *     - File size
+ *     - DNS
+ */
+#define CONFIG_BOOTP_MASK      (CONFIG_BOOTP_DEFAULT | \
+                                CONFIG_BOOTP_BOOTFILESIZE | \
+                                CONFIG_BOOTP_DNS)
+
+/* undef this to save memory */
+#define CFG_LONGHELP
+
+/* Monitor Command Prompt */
+#define CFG_PROMPT             "=> "
+
+/* What ppcboot subsytems do you want enabled? */
+#define CONFIG_COMMANDS                (((CONFIG_CMD_DFL & ~(CFG_CMD_KGDB))) | \
+                               CFG_CMD_ELF     | \
+                               CFG_CMD_ASKENV  | \
+                               CFG_CMD_ECHO    | \
+                               CFG_CMD_I2C     | \
+                               CFG_CMD_REGINFO | \
+                               CFG_CMD_MEMTEST | \
+                               CFG_CMD_MII     | \
+                               CFG_CMD_IMMAP)
+
+
+/* Where do the internal registers live? */
+#define CFG_IMMR               0xf0000000
+
+/*****************************************************************************
+ *
+ * You should not have to modify any of the following settings
+ *
+ *****************************************************************************/
+
+#define CONFIG_MPC8260         1       /* This is an MPC8260 CPU   */
+#define CONFIG_PPMC8260                1       /* on an Wind River PPMC8260 Board  */
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#  define CFG_CBSIZE           1024    /* Console I/O Buffer Size           */
+#else
+#  define CFG_CBSIZE           256     /* Console I/O Buffer Size           */
+#endif
+
+/* Print Buffer Size */
+#define CFG_PBSIZE       (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
+
+#define CFG_MAXARGS            32      /* max number of command args   */
+
+#define CFG_BARGSIZE           CFG_CBSIZE /* Boot Argument Buffer Size    */
+
+#define CFG_LOAD_ADDR          0x140000   /* default load address */
+#define CFG_HZ                 1000    /* decrementer freq: 1 ms ticks */
+
+#define CFG_MEMTEST_START      0x2000  /* memtest works from the end of */
+                                       /* the exception vector table */
+                                       /* to the end of the DRAM  */
+                                       /* less monitor and malloc area */
+#define CFG_STACK_USAGE                0x10000 /* Reserve 64k for the stack usage */
+#define CFG_MEM_END_USAGE      ( CFG_MONITOR_LEN \
+                               + CFG_MALLOC_LEN \
+                               + CFG_ENV_SECT_SIZE \
+                               + CFG_STACK_USAGE )
+
+#define CFG_MEMTEST_END                ( CFG_SDRAM_SIZE * 1024 * 1024 \
+                               - CFG_MEM_END_USAGE )
+
+/* valid baudrates */
+#define CFG_BAUDRATE_TABLE     { 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+
+#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
+/*
+ *  Attention: This is board specific
+ *  - RX clk is CLK11
+ *  - TX clk is CLK12
+ */
+#define CFG_CMXSCR_VALUE       (CMXSCR_RS1CS_CLK11  |\
+                               CMXSCR_TS1CS_CLK12)
+
+#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
+/*
+ * Attention: this is board-specific
+ * - Rx-CLK is CLK13
+ * - Tx-CLK is CLK14
+ * - Select bus for bd/buffers (see 28-13)
+ * - Enable Full Duplex in FSMR
+ */
+#define CFG_CMXFCR_MASK                (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
+#define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
+#define CFG_CPMFCR_RAMTYPE     0
+#define CFG_FCC_PSMR           (FCC_PSMR_FDE | FCC_PSMR_LPB)
+#endif /* CONFIG_ETHER_INDEX */
+
+#define CFG_FLASH_BASE CFG_FLASH0_BASE
+#define CFG_FLASH_SIZE CFG_FLASH0_SIZE
+#define CFG_SDRAM_BASE CFG_SDRAM0_BASE
+#define CFG_SDRAM_SIZE (CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hard Reset Configuration Words
+ */
+#if defined(CFG_PPMC_BOOT_LOW)
+#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
+#else
+#  define  CFG_PPMC_HRCW_BOOT_FLAGS  (0)
+#endif /* defined(CFG_PPMC_BOOT_LOW) */
+
+/* get the HRCW ISB field from CFG_IMMR */
+#define CFG_PPMC_HRCW_IMMR     ( ((CFG_IMMR & 0x10000000) >> 10) | \
+                                 ((CFG_IMMR & 0x01000000) >>  7) | \
+                                 ((CFG_IMMR & 0x00100000) >>  4) )
+
+#define CFG_HRCW_MASTER                ( HRCW_EBM                              | \
+                                 HRCW_BPS11                            | \
+                                 HRCW_L2CPC10                          | \
+                                 HRCW_DPPC00                           | \
+                                 CFG_PPMC_HRCW_IMMR                    | \
+                                 HRCW_MMR00                            | \
+                                 HRCW_LBPC00                           | \
+                                 HRCW_APPC10                           | \
+                                 HRCW_CS10PC00                         | \
+                                 (CFG_PPMC_MODCK_H & HRCW_MODCK_H1111) | \
+                                 CFG_PPMC_HRCW_BOOT_FLAGS )
+
+/* no slaves */
+#define CFG_HRCW_SLAVE1                0
+#define CFG_HRCW_SLAVE2                0
+#define CFG_HRCW_SLAVE3                0
+#define CFG_HRCW_SLAVE4                0
+#define CFG_HRCW_SLAVE5                0
+#define CFG_HRCW_SLAVE6                0
+#define CFG_HRCW_SLAVE7                0
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR      CFG_IMMR
+#define CFG_INIT_RAM_END       0x4000  /* End of used area in DPRAM    */
+#define CFG_INIT_DATA_SIZE     128     /* bytes reserved for initial data */
+#define CFG_INIT_DATA_OFFSET   (CFG_INIT_RAM_END - CFG_INIT_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET     CFG_INIT_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
+ */
+#define CFG_MONITOR_BASE       CFG_FLASH0_BASE
+
+#ifndef CFG_MONITOR_BASE
+#define CFG_MONITOR_BASE       0x0ff80000
+#endif
+
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+#  define CFG_RAMBOOT
+#endif
+
+#define CFG_MONITOR_LEN                (256 << 10)     /* Reserve 374 kB for Monitor   */
+#define CFG_MALLOC_LEN         (128 << 10)     /* Reserve 128 kB for malloc()  */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CFG_BOOTMAPSZ          (8 << 20)       /* Initial Memory map for Linux */
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+#define CFG_FLASH_CFI          1       /* Flash is CFI conformant              */
+#define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip    */
+#define CFG_MAX_FLASH_BANKS    1       /* max number of memory banks           */
+#define CFG_FLASH_INCREMENT    0       /* there is only one bank               */
+#define CFG_FLASH_PROTECTION   1       /* use hardware protection              */
+
+
+#ifndef CFG_RAMBOOT
+
+#  define CFG_ENV_IS_IN_FLASH  1
+#  ifdef CFG_ENV_IN_OWN_SECT
+#    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x60000)
+#    define CFG_ENV_SECT_SIZE  0x20000
+#  else
+#    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
+#    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector     */
+#    define CFG_ENV_SECT_SIZE  0x20000 /* see README - env sect real size      */
+#  endif /* CFG_ENV_IN_OWN_SECT */
+
+#else
+#  define CFG_ENV_IS_IN_FLASH  1
+#  define CFG_ENV_ADDR         (CFG_FLASH_BASE + 0x60000)
+#define CFG_ENV_SIZE           0x1000
+#  define CFG_ENV_SECT_SIZE    0x20000
+#endif /* CFG_RAMBOOT */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE     32      /* For MPC8260 CPU */
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
+#endif
+
+/*-----------------------------------------------------------------------
+ * HIDx - Hardware Implementation-dependent Registers                   2-11
+ *-----------------------------------------------------------------------
+ * HID0 also contains cache control - initially enable both caches and
+ * invalidate contents, then the final state leaves only the instruction
+ * cache enabled. Note that Power-On and Hard reset invalidate the caches,
+ * but Soft reset does not.
+ *
+ * HID1 has only read-only information - nothing to set.
+ */
+#define CFG_HID0_INIT  (HID0_ICE  |\
+                        HID0_DCE  |\
+                        HID0_ICFI |\
+                        HID0_DCI  |\
+                        HID0_IFEM |\
+                        HID0_ABE)
+
+#define CFG_HID0_FINAL (HID0_ICE  |\
+                        HID0_IFEM |\
+                        HID0_ABE  |\
+                        HID0_EMCP)
+#define CFG_HID2       0
+
+/*-----------------------------------------------------------------------
+ * RMR - Reset Mode Register
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RMR                0
+
+/*-----------------------------------------------------------------------
+ * BCR - Bus Configuration                                      4-25
+ *-----------------------------------------------------------------------
+ */
+#define CFG_BCR                (BCR_EBM      |\
+                        0x30000000)
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration                            4-31
+ * Ref Section 4.3.2.6 page 4-31
+ *-----------------------------------------------------------------------
+ */
+
+#define CFG_SIUMCR     (SIUMCR_ESE      |\
+                        SIUMCR_DPPC00   |\
+                        SIUMCR_L2CPC10  |\
+                        SIUMCR_LBPC00   |\
+                        SIUMCR_APPC10   |\
+                        SIUMCR_CS10PC00 |\
+                        SIUMCR_BCTLC00  |\
+                        SIUMCR_MMR00)
+
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control                           11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
+ */
+#define CFG_SYPCR      (SYPCR_SWTC |\
+                        SYPCR_BMT  |\
+                        SYPCR_PBME |\
+                        SYPCR_LBME |\
+                        SYPCR_SWRI |\
+                        SYPCR_SWP)
+
+/*-----------------------------------------------------------------------
+ * TMCNTSC - Time Counter Status and Control                    4-40
+ *-----------------------------------------------------------------------
+ * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
+ * and enable Time Counter
+ */
+#define CFG_TMCNTSC    (TMCNTSC_SEC |\
+                        TMCNTSC_ALR |\
+                        TMCNTSC_TCF |\
+                        TMCNTSC_TCE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control                4-42
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
+ * Periodic timer
+ */
+#define CFG_PISCR      (PISCR_PS  |\
+                        PISCR_PTF |\
+                        PISCR_PTE)
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control                                  9-8
+ *-----------------------------------------------------------------------
+ */
+#define CFG_SCCR       0
+
+/*-----------------------------------------------------------------------
+ * RCCR - RISC Controller Configuration                                13-7
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RCCR       0
+
+/*
+ * Initialize Memory Controller:
+ *
+ * Bank Bus    Machine PortSz  Device
+ * ---- ---    ------- ------  ------
+ *  0  60x     GPCM    32 bit  FLASH (SIMM - 32MB) *
+ *  1  unused
+ *  2  60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
+ *  3  60x     SDRAM   64 bit  SDRAM (DIMM - 128MB)
+ *  4  Local   SDRAM   32 bit  SDRAM (on board - 16MB)
+ *  5  60x     GPCM     8 bit  Mailbox/EEPROM (8KB)
+ *  6  60x     GPCM     8 bit  FLASH  (on board - 2MB) *
+ *  7  60x     GPCM     8 bit  LEDs, switches
+ *
+ *  (*) This configuration requires the PPMC8260 be configured
+ *     so that *CS0 goes to the FLASH SIMM, and *CS6 goes to
+ *     the on board FLASH. In other words, JP24 should have
+ *     pins 1 and 2 jumpered and pins 3 and 4 jumpered.
+ *
+ */
+
+/*-----------------------------------------------------------------------
+ * BR0,BR1 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR0,OR1 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 0,1 - FLASH SIMM
+ *
+ * This expects the FLASH SIMM to be connected to *CS0
+ * It consists of 4 AM29F080B parts.
+ *
+ * Note: For the 4 MB SIMM, *CS1 is unused.
+ */
+
+/* BR0 is configured as follows:
+ *
+ *     - Base address of 0xFE000000
+ *     - 32 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR0_PRELIM ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
+                        BRx_PS_32                      |\
+                        BRx_MS_GPCM_P                  |\
+                        BRx_V)
+
+/* OR0 is configured as follows:
+ *
+ *     - 32 MB
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 5
+ *     - *PSDVAL is generated internally by the memory controller
+ *      unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *      initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *      current bank and the next access.
+ */
+#define CFG_OR0_PRELIM (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
+                        ORxG_CSNT                      |\
+                        ORxG_ACS_DIV1                  |\
+                        ORxG_SCY_5_CLK                 |\
+                        ORxG_TRLX                      |\
+                        ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR2,BR3 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR2,OR3 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 2,3 - 128 MB SDRAM DIMM
+ */
+
+/* With a 128 MB DIMM, the BR2 is configured as follows:
+ *
+ *     - Base address of 0x00000000/0x08000000
+ *     - 64 bit port size (60x bus only)
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - SDRAM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR2_PRELIM ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
+                        BRx_PS_64                      |\
+                        BRx_MS_SDRAM_P                 |\
+                        BRx_V)
+
+#define CFG_BR3_PRELIM ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
+                        BRx_PS_64                      |\
+                        BRx_MS_SDRAM_P                 |\
+                        BRx_V)
+
+/* With a 128 MB DIMM, the OR2 is configured as follows:
+ *
+ *     - 128 MB
+ *     - 4 internal banks per device
+ *     - Row start address bit is A8 with PSDMR[PBI] = 0
+ *     - 13 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CFG_OR2_PRELIM (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI0_A7             |\
+                        ORxS_NUMR_13)
+
+#define CFG_OR3_PRELIM (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI0_A7             |\
+                        ORxS_NUMR_13)
+
+
+/*-----------------------------------------------------------------------
+ * PSDMR - 60x Bus SDRAM Mode Register
+ *     Ref: Section 10.3.3 on page 10-21
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 128 MB DIMM, the PSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A14 pin
+ *      (A6 on A15, and so on),
+ *     - use address pins A13-A15 as bank select,
+ *     - A7 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *      is 3 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *      2 clocks,
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing enabled
+ *     - CAS Latency is 2.
+ */
+#define CFG_PSDMR      (PSDMR_RFEN           |\
+                        PSDMR_SDAM_A14_IS_A5 |\
+                        PSDMR_BSMA_A13_A15   |\
+                        PSDMR_SDA10_PBI0_A9  |\
+                        PSDMR_RFRC_7_CLK     |\
+                        PSDMR_PRETOACT_3W    |\
+                        PSDMR_ACTTORW_2W     |\
+                        PSDMR_LDOTOPRE_1C    |\
+                        PSDMR_WRC_1C         |\
+                        PSDMR_EAMUX          |\
+                        PSDMR_CL_2)
+
+
+#define CFG_PSRT       0x0e
+#define CFG_MPTPR      ( (0x32 << MPTPR_PTP_SHIFT) & MPTPR_PTP_MSK)
+
+
+/*-----------------------------------------------------------------------
+ * BR4 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR4 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 4 - On board SDRAM
+ *
+ */
+/* With 16 MB of onboard SDRAM BR4 is configured as follows
+ *
+ *     - Base address 0x38000000
+ *     - 32 bit port size
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - SDRAM local bus
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ *
+ */
+
+#define CFG_BR4_PRELIM ((CFG_SDRAM2_BASE & BRx_BA_MSK) |\
+                        BRx_PS_32                      |\
+                        BRx_DECC_NONE                  |\
+                        BRx_MS_SDRAM_L                 |\
+                        BRx_V)
+
+/*
+ * With 16MB SDRAM, OR4 is configured as follows
+ *     - 4 internal banks per device
+ *     - Row start address bit is A7 with LSDMR[PBI] = 0
+ *     - 13 row address lines
+ *     - Back-to-back page mode
+ *     - Internal bank interleaving within save device enabled
+ */
+
+#define CFG_OR4_PRELIM (MEG_TO_AM(CFG_SDRAM2_SIZE)     |\
+                        ORxS_BPD_4                     |\
+                        ORxS_ROWST_PBI0_A10            |\
+                        ORxS_NUMR_12)
+
+
+/*-----------------------------------------------------------------------
+ * LSDMR - Local Bus SDRAM Mode Register
+ *     Ref: Section 10.3.4 on page 10-24
+ *-----------------------------------------------------------------------
+ */
+
+/* With a 16 MB onboard SDRAM, the LSDMR is configured as follows:
+ *
+ *     - Page Based Interleaving,
+ *     - Refresh Enable,
+ *     - Normal Operation
+ *     - Address Multiplexing where A5 is output on A13 pin
+ *      (A6 on A15, and so on),
+ *     - use address pins A15-A17 as bank select,
+ *     - A11 is output on SDA10 during an ACTIVATE command,
+ *     - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
+ *     - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
+ *      is 2 clocks,
+ *     - earliest timing for READ/WRITE command after ACTIVATE command is
+ *      2 clocks,
+ *     - SDRAM burst length is 8
+ *     - earliest timing for PRECHARGE after last data was read is 1 clock,
+ *     - earliest timing for PRECHARGE after last data was written is 1 clock,
+ *     - External Address Multiplexing disabled
+ *     - CAS Latency is 2.
+ */
+#define CFG_LSDMR      (PSDMR_RFEN           |\
+                        PSDMR_SDAM_A13_IS_A5 |\
+                        PSDMR_BSMA_A15_A17   |\
+                        PSDMR_SDA10_PBI0_A11 |\
+                        PSDMR_RFRC_7_CLK     |\
+                        PSDMR_PRETOACT_2W    |\
+                        PSDMR_ACTTORW_2W     |\
+                        PSDMR_BL             |\
+                        PSDMR_LDOTOPRE_1C    |\
+                        PSDMR_WRC_1C         |\
+                        PSDMR_CL_2)
+
+#define CFG_LSRT       0x0e
+
+/*-----------------------------------------------------------------------
+ * BR5 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR5 - Option Register
+ *     Ref: Section 10.3.2 on page 10-16
+ *-----------------------------------------------------------------------
+ */
+
+/*
+ * Bank 5 EEProm and Mailbox
+ *
+ * The EEPROM and mailbox live on the same chip select.
+ * the eeprom is selected if the MSb of the address is set and the mailbox is
+ * selected if the MSb of the address is clear.
+ *
+ */
+
+/* BR5 is configured as follows:
+ *
+ *     - Base address of 0x32000000/0xF2000000
+ *     - 8 bit
+ *     - Data error checking disabled
+ *     - Read/Write access
+ *     - GPCM 60x Bus
+ *     - SDRAM local bus
+ *     - No data pipelining is done
+ *     - Valid
+ */
+
+#define CFG_BR5_PRELIM ((CFG_MAILBOX_BASE & BRx_BA_MSK) |\
+                        BRx_PS_8                        |\
+                        BRx_DECC_NONE                   |\
+                        BRx_MS_GPCM_P                   |\
+                        BRx_V)
+/* OR5 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *      unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *      initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *      current bank and the next access.
+ */
+
+#define CFG_OR5_PRELIM ((P2SZ_TO_AM(CFG_MAILBOX_SIZE) & ~0x80000000) |\
+                        ORxG_ACS_DIV2                               |\
+                        ORxG_SCY_15_CLK                             |\
+                        ORxG_TRLX                                   |\
+                        ORxG_EHTR)
+
+/*-----------------------------------------------------------------------
+ * BR6 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR6 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 6 - I/O select
+ *
+ */
+
+/* BR6 is configured as follows:
+ *
+ *     - Base address of 0xE0000000
+ *     - 16 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR6_PRELIM ((CFG_IOSELECT_BASE & BRx_BA_MSK) |\
+                          BRx_PS_16                      |\
+                          BRx_MS_GPCM_P                  |\
+                          BRx_V)
+
+/* OR6 is configured as follows
+ *     - buffer control enabled
+ *     - chip select negated normally
+ *     - CS output 1/2 clock after address
+ *     - 15 wait states
+ *     - *PSDVAL is generated internally by the memory controller
+ *      unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *      initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *      current bank and the next access.
+ */
+
+#define CFG_OR6_PRELIM (MEG_TO_AM(CFG_IOSELECT_SIZE) |\
+                        ORxG_ACS_DIV2               |\
+                        ORxG_SCY_15_CLK             |\
+                        ORxG_TRLX                   |\
+                        ORxG_EHTR)
+
+
+/*-----------------------------------------------------------------------
+ * BR7 - Base Register
+ *     Ref: Section 10.3.1 on page 10-14
+ * OR7 - Option Register
+ *     Ref: Section 10.3.2 on page 10-18
+ *-----------------------------------------------------------------------
+ */
+
+/* Bank 7 - LEDs and switches
+ *
+ *  LEDs     are at 0x00001 (write only)
+ *  switches are at 0x00001 (read only)
+ */
+#ifdef CFG_LED_BASE
+
+/* BR7 is configured as follows:
+ *
+ *     - Base address of 0xA0000000
+ *     - 8 bit port size
+ *     - Data errors checking is disabled
+ *     - Read and write access
+ *     - GPCM 60x bus
+ *     - Access are handled by the memory controller according to MSEL
+ *     - Not used for atomic operations
+ *     - No data pipelining is done
+ *     - Valid
+ */
+#define CFG_BR7_PRELIM ((CFG_LED_BASE & BRx_BA_MSK)     |\
+                          BRx_PS_8                      |\
+                          BRx_DECC_NONE                 |\
+                          BRx_MS_GPCM_P                 |\
+                          BRx_V)
+
+/* OR7 is configured as follows:
+ *
+ *     - 1 byte
+ *     - *BCTL0 is asserted upon access to the current memory bank
+ *     - *CW / *WE are negated a quarter of a clock earlier
+ *     - *CS is output at the same time as the address lines
+ *     - Uses a clock cycle length of 15
+ *     - *PSDVAL is generated internally by the memory controller
+ *      unless *GTA is asserted earlier externally.
+ *     - Relaxed timing is generated by the GPCM for accesses
+ *      initiated to this memory region.
+ *     - One idle clock is inserted between a read access from the
+ *      current bank and the next access.
+ */
+#define CFG_OR7_PRELIM (ORxG_AM_MSK                   |\
+                        ORxG_CSNT                     |\
+                        ORxG_ACS_DIV1                 |\
+                        ORxG_SCY_15_CLK               |\
+                        ORxG_TRLX                     |\
+                        ORxG_EHTR)
+#endif /* CFG_LED_BASE */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD  0x01    /* Normal Power-On: Boot from FLASH  */
+#define BOOTFLAG_WARM  0x02    /* Software reboot                   */
+
+#endif /* __CONFIG_H */

diff --git a/include/flash.h b/include/flash.h
index f08f3024e5a8066f33fafc9337639ec7ac7b47f7..b2802116818c88c3f529ab8dbbeacccc9547c5f7 100644 (file)
--- a/include/flash.h
+++ b/include/flash.h
@@ -34,8 +34,29 @@ typedef struct {
        ulong   flash_id;               /* combined device & manufacturer code  */
        ulong   start[CFG_MAX_FLASH_SECT];   /* physical sector start addresses */
        uchar   protect[CFG_MAX_FLASH_SECT]; /* sector protection status        */
+#ifdef CFG_FLASH_CFI
+       uchar   portwidth;              /* the width of the port                */
+       uchar   chipwidth;              /* the width of the chip                */
+       ulong   erase_blk_tout;         /* maximum block erase timeout          */
+       ulong   write_tout;             /* maximum write timeout                */
+#endif
 } flash_info_t;
 
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT         0x01
+#define FLASH_CFI_16BIT                0x02
+#define FLASH_CFI_32BIT                0x04
+#define FLASH_CFI_64BIT                0x08
+/*
+ * Values for the width of the chip
+ */
+#define FLASH_CFI_BY8          0x01
+#define FLASH_CFI_BY16         0x02
+#define FLASH_CFI_BY32         0x04
+#define FLASH_CFI_BY64         0x08
+
 /* Prototypes */
 
 extern unsigned long flash_init (void);
@@ -136,13 +157,19 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define INTEL_ID_28F160B3T  0x88908890 /*  16M = 1M x 16 top boot sector       */
 #define INTEL_ID_28F160B3B  0x88918891 /*  16M = 1M x 16 bottom boot sector    */
 #define INTEL_ID_28F320B3T  0x88968896 /*  32M = 2M x 16 top boot sector       */
-#define INTEL_ID_28F320C3T  0x88C488C4 /*  32M = 2M x 16 top boot sector       */
 #define INTEL_ID_28F320B3B  0x88978897 /*  32M = 2M x 16 bottom boot sector    */
 #define INTEL_ID_28F640B3T  0x88988898 /*  64M = 4M x 16 top boot sector       */
 #define INTEL_ID_28F640B3B  0x88998899 /*  64M = 4M x 16 bottom boot sector    */
-#define INTEL_ID_28F160C3B  0x88C388C3 /*  16M = 1M x 16 bottom boot sector    */
 #define INTEL_ID_28F160F3B  0x88F488F4 /*  16M = 1M x 16 bottom boot sector    */
-#define INTEL_ID_28F320C3   0x88C588C5 /*   4MB , 8 8KB + 63 64KB bbt          */
+
+#define INTEL_ID_28F800C3T  0x88C088C0 /*  8M = 512K x 16 top boot sector      */
+#define INTEL_ID_28F800C3B  0x88C188C1 /*  8M = 512K x 16 bottom boot sector   */
+#define INTEL_ID_28F160C3T  0x88C288C2 /*  16M = 1M x 16 top boot sector       */
+#define INTEL_ID_28F160C3B  0x88C388C3 /*  16M = 1M x 16 bottom boot sector    */
+#define INTEL_ID_28F320C3T  0x88C488C4 /*  32M = 2M x 16 top boot sector       */
+#define INTEL_ID_28F320C3B  0x88C588C5 /*  32M = 2M x 16 bottom boot sector    */
+#define INTEL_ID_28F640C3T  0x88CC88CC /*  64M = 4M x 16 top boot sector       */
+#define INTEL_ID_28F640C3B  0x88CD88CD /*  64M = 4M x 16 bottom boot sector    */
 
 #define INTEL_ID_28F640J5   0x00150015 /*  64M = 128K x  64                    */
 #define INTEL_ID_28F320J3A  0x00160016 /*  32M = 128K x  32                    */
@@ -218,16 +245,22 @@ extern int flash_real_protect(flash_info_t *info, long sector, int prot);
 #define FLASH_28F320J5 0x0085          /* Intel 28F320J5  (  4M = 128K x 32 )  */
 #define FLASH_28F160S3 0x0086          /* Intel 28F160S3  ( 16M = 512K x 32 )  */
 #define FLASH_28F320S3 0x0088          /* Intel 28F320S3  ( 32M = 512K x 64 )  */
-#define FLASH_28F320C3 0x0089          /* Intel 28F320C3  ( 32M = 64Kx8 + 512x64)*/
 #define FLASH_AM640U   0x0090          /* AMD Am29LV640U  ( 64M = 4M x 16 )    */
 #define FLASH_AM033C   0x0091          /* AMD AM29LV033   ( 32M = 4M x 8 )     */
-#define FLASH_28F160C3B        0x0091          /* Intel 28F160C3B ( 16M = 1M x 16 )    */
-#define FLASH_28F160F3B        0x0093          /* Intel 28F160F3B ( 16M = 1M x 16 )    */
-
 #define FLASH_LH28F016SCT 0x0092       /* Sharp 28F016SCT ( 8 Meg Flash SIMM ) */
+#define FLASH_28F160F3B        0x0093          /* Intel 28F160F3B ( 16M = 1M x 16 )    */
 
 #define FLASH_28F640J5  0x0099         /* INTEL 28F640J5  ( 64M = 128K x  64)  */
 
+#define FLASH_28F800C3T        0x009A          /* Intel 28F800C3T (  8M = 512K x 16 )  */
+#define FLASH_28F800C3B        0x009B          /* Intel 28F800C3B (  8M = 512K x 16 )  */
+#define FLASH_28F160C3T        0x009C          /* Intel 28F160C3T ( 16M = 1M x 16 )    */
+#define FLASH_28F160C3B        0x009D          /* Intel 28F160C3B ( 16M = 1M x 16 )    */
+#define FLASH_28F320C3T        0x009E          /* Intel 28F320C3T ( 32M = 2M x 16 )    */
+#define FLASH_28F320C3B        0x009F          /* Intel 28F320C3B ( 32M = 2M x 16 )    */
+#define FLASH_28F640C3T        0x00A0          /* Intel 28F640C3T ( 64M = 4M x 16 )    */
+#define FLASH_28F640C3B        0x00A1          /* Intel 28F640C3B ( 64M = 4M x 16 )    */
+
 #define FLASH_UNKNOWN  0xFFFF          /* unknown flash type                   */
 
 

diff --git a/include/ppcboot.h b/include/ppcboot.h
index 683cf5c51c6947b962d37da18ee0e5347c66c457..dffbee90dbf94516a42d7cbda264fc8dceba68c3 100644 (file)
--- a/include/ppcboot.h
+++ b/include/ppcboot.h
@@ -334,7 +334,7 @@ void        load_sernum_ethaddr(bd_t *bd);
 /* $(BOARD)/$(BOARD).c */
 int    board_pre_init (void);
 #endif
-#if defined(CONFIG_HYMOD)
+#if defined(CONFIG_HYMOD) || defined(CONFIG_BOARD_POSTCLK_INIT)
 void   board_postclk_init(void); /* after clocks/timebase, before env/serial */
 #endif
 #if defined(CFG_DRAM_TEST)

diff --git a/rtc/Makefile b/rtc/Makefile
index a255f113aca814fbe90780a7bdc8ed8ea2f8f4d3..a621a15bfd3f492b9edee71b25ef1b2c55915861 100644 (file)
--- a/rtc/Makefile
+++ b/rtc/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB    = librtc.a
 
-OBJS   = date.o   ds1302.o ds174x.o \
+OBJS   = date.o   ds1302.o ds174x.o ds1306.o \
          m48t35ax.o mc146818.o mk48t59.o mpc8xx.o pcf8563.o
 
 all:   $(LIB)

diff --git a/rtc/ds1306.c b/rtc/ds1306.c
new file mode 100644 (file)
index 0000000..fa966ee
--- /dev/null
+++ b/rtc/ds1306.c
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2002 SIXNET, dge@sixnetio.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for DS1306 RTC using software SPI
+ */
+
+#include <ppcboot.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_RTC_DS1306) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+static unsigned int bin2bcd(unsigned int n);
+static unsigned char bcd2bin(unsigned char c);
+static void soft_spi_send(unsigned char n);
+static unsigned char soft_spi_read(void);
+static void init_spi(void);
+
+/*-----------------------------------------------------------------------
+ * Definitions
+ */
+
+#define        PB_SPISCK       0x00000002      /* PB 30 */
+#define PB_SPIMOSI     0x00000004      /* PB 29 */
+#define PB_SPIMISO     0x00000008      /* PB 28 */
+#define PB_SPI_CE      0x00010000      /* PB 15 */
+
+/* ------------------------------------------------------------------------- */
+
+/* read clock time from DS1306 and return it in *tmp */
+void rtc_get(struct rtc_time *tmp)
+{
+    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+    unsigned char spi_byte;    /* Data Byte */
+
+    init_spi();                /* set port B for software SPI */
+
+    /* Now we can enable the DS1306 RTC */
+    immap->im_cpm.cp_pbdat |= PB_SPI_CE;
+    udelay(10);
+
+    /* Shift out the address (0) of the time in the Clock Chip */
+    soft_spi_send(0);
+
+    /* Put the clock readings into the rtc_time structure */
+    tmp->tm_sec = bcd2bin(soft_spi_read());    /* Read seconds */
+    tmp->tm_min = bcd2bin(soft_spi_read());    /* Read minutes */
+
+    /* Hours are trickier */
+    spi_byte = soft_spi_read();        /* Read Hours into temporary value */
+    if (spi_byte & 0x40) {
+       /* 12 hour mode bit is set (time is in 1-12 format) */
+       if (spi_byte & 0x20) {
+           /* since PM we add 11 to get 0-23 for hours */
+           tmp->tm_hour = (bcd2bin(spi_byte & 0x1F)) + 11;
+       }
+       else {
+           /* since AM we subtract 1 to get 0-23 for hours */
+           tmp->tm_hour = (bcd2bin(spi_byte & 0x1F)) - 1;
+       }
+    }
+    else {
+       /* Otherwise, 0-23 hour format */
+       tmp->tm_hour = (bcd2bin(spi_byte & 0x3F));
+    }
+
+    soft_spi_read();           /* Read and discard Day of week */
+    tmp->tm_mday = bcd2bin(soft_spi_read());   /* Read Day of the Month */
+    tmp->tm_mon = bcd2bin(soft_spi_read());    /* Read Month */
+
+    /* Read Year and convert to this century */
+    tmp->tm_year = bcd2bin(soft_spi_read()) + 2000;
+
+    /* Now we can disable the DS1306 RTC */
+    immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;      /* Disable DS1306 Chip */
+    udelay(10);
+
+    GregorianDay(tmp);         /* Determine the day of week */
+
+    debug("Get DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+         tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+         tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* set clock time in DS1306 RTC and in MPC8xx RTC */
+void rtc_set(struct rtc_time *tmp)
+{
+    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+    init_spi();                /* set port B for software SPI */
+
+    /* Now we can enable the DS1306 RTC */
+    immap->im_cpm.cp_pbdat |= PB_SPI_CE;       /* Enable DS1306 Chip */
+    udelay(10);
+
+    /* First disable write protect in the clock chip control register */
+    soft_spi_send(0x8F);       /* send address of the control register */
+    soft_spi_send(0x00);       /* send control register contents */
+
+    /* Now disable the DS1306 to terminate the write */
+    immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;
+    udelay(10);
+
+    /* Now enable the DS1306 to initiate a new write */
+    immap->im_cpm.cp_pbdat |= PB_SPI_CE;
+    udelay(10);
+
+    /* Next, send the address of the clock time write registers */
+    soft_spi_send(0x80);       /* send address of the first time register */
+
+    /* Use Burst Mode to send all of the time data to the clock */
+    bin2bcd(tmp->tm_sec);
+    soft_spi_send(bin2bcd(tmp->tm_sec));       /* Send Seconds */
+    soft_spi_send(bin2bcd(tmp->tm_min));       /* Send Minutes */
+    soft_spi_send(bin2bcd(tmp->tm_hour));      /* Send Hour */
+    soft_spi_send(bin2bcd(tmp->tm_wday));      /* Send Day of the Week */
+    soft_spi_send(bin2bcd(tmp->tm_mday));      /* Send Day of Month */
+    soft_spi_send(bin2bcd(tmp->tm_mon));       /* Send Month */
+    soft_spi_send(bin2bcd(tmp->tm_year - 2000));       /* Send Year */
+
+    /* Now we can disable the Clock chip to terminate the burst write */
+    immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;      /* Disable DS1306 Chip */
+    udelay(10);
+
+    /* Now we can enable the Clock chip to initiate a new write */
+    immap->im_cpm.cp_pbdat |= PB_SPI_CE;       /* Enable DS1306 Chip */
+    udelay(10);
+
+    /* First we Enable write protect in the clock chip control register */
+    soft_spi_send(0x8F);       /* send address of the control register */
+    soft_spi_send(0x40);       /* send out Control Register contents */
+
+    /* Now disable the DS1306 */
+    immap->im_cpm.cp_pbdat &= ~PB_SPI_CE;      /*  Disable DS1306 Chip */
+    udelay(10);
+
+    /* Set standard MPC8xx clock to the same time so Linux will
+     * see the time even if it doesn't have a DS1306 clock driver.
+     * This helps with experimenting with standard kernels.
+     */
+    {
+       ulong tim;
+
+       tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
+                    tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+       immap->im_sitk.sitk_rtck = KAPWR_KEY;
+       immap->im_sit.sit_rtc = tim;
+    }
+
+    debug("Set DATE: %4d-%02d-%02d (wday=%d)  TIME: %2d:%02d:%02d\n",
+         tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+         tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+}
+
+/* ------------------------------------------------------------------------- */
+
+void rtc_reset(void)
+{
+    return;                    /* nothing to do */
+}
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned char bcd2bin(unsigned char n)
+{
+    return ((((n >> 4) & 0x0F) * 10) + (n & 0x0F));
+}
+
+/* ------------------------------------------------------------------------- */
+
+static unsigned int bin2bcd(unsigned int n)
+{
+    return (((n / 10) << 4) | (n % 10));
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* Initialize Port B for software SPI */
+static void init_spi(void) {
+    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+    /* Force output pins to begin at logic 0 */
+    immap->im_cpm.cp_pbdat &= ~(PB_SPI_CE | PB_SPIMOSI | PB_SPISCK);
+
+    /* Set these 3 signals as outputs */
+    immap->im_cpm.cp_pbdir |= (PB_SPIMOSI | PB_SPI_CE | PB_SPISCK);
+
+    immap->im_cpm.cp_pbdir &= ~PB_SPIMISO;     /* Make MISO pin an input */
+    udelay(10);
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* NOTE: soft_spi_send() assumes that the I/O lines are configured already */
+static void soft_spi_send(unsigned char n)
+{
+    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+    unsigned char bitpos;      /* bit position to receive */
+    unsigned char i;           /* Loop Control */
+
+    /* bit position to send, start with most significant bit */
+    bitpos = 0x80;
+
+    /* Send 8 bits to software SPI */
+    for (i = 0; i < 8; i++) {  /* Loop for 8 bits */
+       immap->im_cpm.cp_pbdat |= PB_SPISCK;    /* Raise SCK */
+
+       if (n & bitpos)
+           immap->im_cpm.cp_pbdat |= PB_SPIMOSI;       /* Set MOSI to 1 */
+       else
+           immap->im_cpm.cp_pbdat &= ~PB_SPIMOSI;      /* Set MOSI to 0 */
+       udelay(10);
+
+       immap->im_cpm.cp_pbdat &= ~PB_SPISCK;   /* Lower SCK */
+       udelay(10);
+
+       bitpos >>= 1;           /* Shift for next bit position */
+    }
+}
+
+/* ------------------------------------------------------------------------- */
+
+/* NOTE: soft_spi_read() assumes that the I/O lines are configured already */
+static unsigned char soft_spi_read(void)
+{
+    volatile immap_t *immap = (immap_t *)CFG_IMMR;
+
+    unsigned char spi_byte = 0;        /* Return value, assume success */
+    unsigned char bitpos;      /* bit position to receive */
+    unsigned char i;           /* Loop Control */
+
+    /* bit position to receive, start with most significant bit */
+    bitpos = 0x80;
+
+    /* Read 8 bits here */
+    for (i = 0; i < 8; i++) {  /* Do 8 bits in loop */
+       immap->im_cpm.cp_pbdat |= PB_SPISCK;    /* Raise SCK */
+       udelay(10);
+       if (immap->im_cpm.cp_pbdat & PB_SPIMISO)        /* Get a bit of data */
+           spi_byte |= bitpos; /* Set data accordingly */
+       immap->im_cpm.cp_pbdat &= ~PB_SPISCK;   /* Lower SCK */
+       udelay(10);
+       bitpos >>= 1;           /* Shift for next bit position */
+    }
+
+    return spi_byte;           /* Return the byte read */
+}
+
+/* ------------------------------------------------------------------------- */
+
+#endif