drm/amd/display: dal1.1 hwseq prog update

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 223bb79bc8b814bae5cd2b60e08403d56c1a5070..4c39bf052d08f9ae40c90ba5b2da59753e0420f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -64,17 +64,13 @@ static void enable_dppclk(
                        plane_id,
                        dppclk_div);
 
-       if (dppclk_div) {
-               /* 1/2 DISPCLK*/
+       if (hws->shifts->DPPCLK_RATE_CONTROL)
                REG_UPDATE_2(DPP_CONTROL[plane_id],
-                       DPPCLK_RATE_CONTROL, 1,
+                       DPPCLK_RATE_CONTROL, dppclk_div,
                        DPP_CLOCK_ENABLE, 1);
-       } else {
-               /* DISPCLK */
-               REG_UPDATE_2(DPP_CONTROL[plane_id],
-                       DPPCLK_RATE_CONTROL, 0,
+       else
+               REG_UPDATE(DPP_CONTROL[plane_id],
                        DPP_CLOCK_ENABLE, 1);
-       }
 }
 
 static void enable_power_gating_plane(