mmc: sdhci-cadence: fix bit shift of read data from PHY port

This macro is currently unused, but it may be useful for debug use.
Fix it just in case.

Fixes: ff6af28faff5 ("mmc: sdhci-cadence: add Cadence SD4HC support")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
index 31e786d1b71ab2a52606a96c38ba2dad0e912125..316cfec3f0050a988e42d50129479b58bca233ae 100644 (file)
--- a/drivers/mmc/host/sdhci-cadence.c
+++ b/drivers/mmc/host/sdhci-cadence.c
@@ -26,7 +26,7 @@
 #define   SDHCI_CDNS_HRS04_ACK                 BIT(26)
 #define   SDHCI_CDNS_HRS04_RD                  BIT(25)
 #define   SDHCI_CDNS_HRS04_WR                  BIT(24)
-#define   SDHCI_CDNS_HRS04_RDATA_SHIFT         12
+#define   SDHCI_CDNS_HRS04_RDATA_SHIFT         16
 #define   SDHCI_CDNS_HRS04_WDATA_SHIFT         8
 #define   SDHCI_CDNS_HRS04_ADDR_SHIFT          0