platform/x86/intel/pmc: Retrieve LPM information using Intel PMT

On supported platforms, the low power mode (LPM) requirements for entering
each idle substate are described in Platform Monitoring Technology (PMT)
telemetry entries. Provide a function for platform code to attempt to find
and read the requirements from the telemetry entries.

Signed-off-by: Xi Pardee <xi.pardee@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Link: https://lore.kernel.org/r/20231129222132.2331261-18-david.e.box@linux.intel.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/intel/pmc/core.h b/drivers/platform/x86/intel/pmc/core.h
index edaa70067e41e26941da6039862a704af74a4491..85b6f6ae4995d1fcec3ef96e49d58e02265b8ff1 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core.h
+++ b/drivers/platform/x86/intel/pmc/core.h
@@ -320,6 +320,7 @@ struct pmc_reg_map {
        const u32 lpm_status_offset;
        const u32 lpm_live_status_offset;
        const u32 etr3_offset;
+       const u8  *lpm_reg_index;
 };
 
 /**
@@ -329,6 +330,7 @@ struct pmc_reg_map {
  *                     specific attributes
  */
 struct pmc_info {
+       u32 guid;
        u16 devid;
        const struct pmc_reg_map *map;
 };
@@ -486,6 +488,7 @@ extern const struct pmc_bit_map *mtl_ioem_lpm_maps[];
 extern const struct pmc_reg_map mtl_ioem_reg_map;
 
 extern void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev);
+extern int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev);
 extern int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value);
 
 int pmc_core_resume_common(struct pmc_dev *pmcdev);

diff --git a/drivers/platform/x86/intel/pmc/core_ssram.c b/drivers/platform/x86/intel/pmc/core_ssram.c
index 9ca720f9cbb233be4a3bfa0d72d0c234b28eb1a3..3501c7bd6b336adc7c5263b42a0db893a6ec8b62 100644 (file)
--- a/drivers/platform/x86/intel/pmc/core_ssram.c
+++ b/drivers/platform/x86/intel/pmc/core_ssram.c
@@ -24,8 +24,142 @@
 #define SSRAM_IOE_OFFSET       0x68
 #define SSRAM_DEVID_OFFSET     0x70
 
+/* PCH query */
+#define LPM_HEADER_OFFSET      1
+#define LPM_REG_COUNT          28
+#define LPM_MODE_OFFSET                1
+
 DEFINE_FREE(pmc_core_iounmap, void __iomem *, iounmap(_T));
 
+static u32 pmc_core_find_guid(struct pmc_info *list, const struct pmc_reg_map *map)
+{
+       for (; list->map; ++list)
+               if (list->map == map)
+                       return list->guid;
+
+       return 0;
+}
+
+static int pmc_core_get_lpm_req(struct pmc_dev *pmcdev, struct pmc *pmc)
+{
+       struct telem_endpoint *ep;
+       const u8 *lpm_indices;
+       int num_maps, mode_offset = 0;
+       int ret, mode, i;
+       int lpm_size;
+       u32 guid;
+
+       lpm_indices = pmc->map->lpm_reg_index;
+       num_maps = pmc->map->lpm_num_maps;
+       lpm_size = LPM_MAX_NUM_MODES * num_maps;
+
+       guid = pmc_core_find_guid(pmcdev->regmap_list, pmc->map);
+       if (!guid)
+               return -ENXIO;
+
+       ep = pmt_telem_find_and_register_endpoint(pmcdev->ssram_pcidev, guid, 0);
+       if (IS_ERR(ep)) {
+               dev_dbg(&pmcdev->pdev->dev, "couldn't get telem endpoint %ld",
+                       PTR_ERR(ep));
+               return -EPROBE_DEFER;
+       }
+
+       pmc->lpm_req_regs = devm_kzalloc(&pmcdev->pdev->dev,
+                                        lpm_size * sizeof(u32),
+                                        GFP_KERNEL);
+       if (!pmc->lpm_req_regs) {
+               ret = -ENOMEM;
+               goto unregister_ep;
+       }
+
+       /*
+        * PMC Low Power Mode (LPM) table
+        *
+        * In telemetry space, the LPM table contains a 4 byte header followed
+        * by 8 consecutive mode blocks (one for each LPM mode). Each block
+        * has a 4 byte header followed by a set of registers that describe the
+        * IP state requirements for the given mode. The IP mapping is platform
+        * specific but the same for each block, making for easy analysis.
+        * Platforms only use a subset of the space to track the requirements
+        * for their IPs. Callers provide the requirement registers they use as
+        * a list of indices. Each requirement register is associated with an
+        * IP map that's maintained by the caller.
+        *
+        * Header
+        * +----+----------------------------+----------------------------+
+        * |  0 |      REVISION              |      ENABLED MODES         |
+        * +----+--------------+-------------+-------------+--------------+
+        *
+        * Low Power Mode 0 Block
+        * +----+--------------+-------------+-------------+--------------+
+        * |  1 |     SUB ID   |     SIZE    |   MAJOR     |   MINOR      |
+        * +----+--------------+-------------+-------------+--------------+
+        * |  2 |           LPM0 Requirements 0                           |
+        * +----+---------------------------------------------------------+
+        * |    |                  ...                                    |
+        * +----+---------------------------------------------------------+
+        * | 29 |           LPM0 Requirements 27                          |
+        * +----+---------------------------------------------------------+
+        *
+        * ...
+        *
+        * Low Power Mode 7 Block
+        * +----+--------------+-------------+-------------+--------------+
+        * |    |     SUB ID   |     SIZE    |   MAJOR     |   MINOR      |
+        * +----+--------------+-------------+-------------+--------------+
+        * | 60 |           LPM7 Requirements 0                           |
+        * +----+---------------------------------------------------------+
+        * |    |                  ...                                    |
+        * +----+---------------------------------------------------------+
+        * | 87 |           LPM7 Requirements 27                          |
+        * +----+---------------------------------------------------------+
+        *
+        */
+       mode_offset = LPM_HEADER_OFFSET + LPM_MODE_OFFSET;
+       pmc_for_each_mode(i, mode, pmcdev) {
+               u32 *req_offset = pmc->lpm_req_regs + (mode * num_maps);
+               int m;
+
+               for (m = 0; m < num_maps; m++) {
+                       u8 sample_id = lpm_indices[m] + mode_offset;
+
+                       ret = pmt_telem_read32(ep, sample_id, req_offset, 1);
+                       if (ret) {
+                               dev_err(&pmcdev->pdev->dev,
+                                       "couldn't read Low Power Mode requirements: %d\n", ret);
+                               devm_kfree(&pmcdev->pdev->dev, pmc->lpm_req_regs);
+                               goto unregister_ep;
+                       }
+                       ++req_offset;
+               }
+               mode_offset += LPM_REG_COUNT + LPM_MODE_OFFSET;
+       }
+
+unregister_ep:
+       pmt_telem_unregister_endpoint(ep);
+
+       return ret;
+}
+
+int pmc_core_ssram_get_lpm_reqs(struct pmc_dev *pmcdev)
+{
+       int ret, i;
+
+       if (!pmcdev->ssram_pcidev)
+               return -ENODEV;
+
+       for (i = 0; i < ARRAY_SIZE(pmcdev->pmcs); ++i) {
+               if (!pmcdev->pmcs[i])
+                       continue;
+
+               ret = pmc_core_get_lpm_req(pmcdev, pmcdev->pmcs[i]);
+               if (ret)
+                       return ret;
+       }
+
+       return 0;
+}
+
 static void
 pmc_add_pmt(struct pmc_dev *pmcdev, u64 ssram_base, void __iomem *ssram)
 {
@@ -189,3 +323,4 @@ release_dev:
        return ret;
 }
 MODULE_IMPORT_NS(INTEL_VSEC);
+MODULE_IMPORT_NS(INTEL_PMT_TELEMETRY);