intel_th: Update scratchpad bits according to enabled output activity

Intel TH implements a scratchpad register to indicate to the firmware
and external debuggers what trace configuration is enabled so that
everybody plays nicely together. The register is a bit field and the
bit assignment convention is described in the developer's manual.

This patch enables the driver to automatically set scratchpad register
bits according to the output configuration that's enabled.

Based on work by Yann Fouassier.

Signed-off-by: Yann Fouassier <yann.fouassier@intel.com>
Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/hwtracing/intel_th/core.c b/drivers/hwtracing/intel_th/core.c
index 165d3001c3015466e605b092358820bbe4327e64..b8b9895da5d18d8982cc5e46e24a2db1f2eca036 100644 (file)
--- a/drivers/hwtracing/intel_th/core.c
+++ b/drivers/hwtracing/intel_th/core.c
@@ -319,6 +319,7 @@ static struct intel_th_subdevice {
        unsigned                nres;
        unsigned                type;
        unsigned                otype;
+       unsigned                scrpd;
        int                     id;
 } intel_th_subdevices[TH_SUBDEVICE_MAX] = {
        {
@@ -352,6 +353,7 @@ static struct intel_th_subdevice {
                .id     = 0,
                .type   = INTEL_TH_OUTPUT,
                .otype  = GTH_MSU,
+               .scrpd  = SCRPD_MEM_IS_PRIM_DEST | SCRPD_MSC0_IS_ENABLED,
        },
        {
                .nres   = 2,
@@ -371,6 +373,7 @@ static struct intel_th_subdevice {
                .id     = 1,
                .type   = INTEL_TH_OUTPUT,
                .otype  = GTH_MSU,
+               .scrpd  = SCRPD_MEM_IS_PRIM_DEST | SCRPD_MSC1_IS_ENABLED,
        },
        {
                .nres   = 2,
@@ -403,6 +406,7 @@ static struct intel_th_subdevice {
                .name   = "pti",
                .type   = INTEL_TH_OUTPUT,
                .otype  = GTH_PTI,
+               .scrpd  = SCRPD_PTI_IS_PRIM_DEST,
        },
        {
                .nres   = 1,
@@ -477,6 +481,7 @@ static int intel_th_populate(struct intel_th *th, struct resource *devres,
                        thdev->dev.devt = MKDEV(th->major, i);
                        thdev->output.type = subdev->otype;
                        thdev->output.port = -1;
+                       thdev->output.scratchpad = subdev->scrpd;
                }
 
                err = device_add(&thdev->dev);

diff --git a/drivers/hwtracing/intel_th/gth.c b/drivers/hwtracing/intel_th/gth.c
index e4c9811c1f400ceabb8b73f7bd17f117299feb9a..9beea0b54231f720bea4570ad56a6a54665b55f6 100644 (file)
--- a/drivers/hwtracing/intel_th/gth.c
+++ b/drivers/hwtracing/intel_th/gth.c
@@ -286,6 +286,10 @@ static int intel_th_gth_reset(struct gth_device *gth)
        if (scratchpad & SCRPD_DEBUGGER_IN_USE)
                return -EBUSY;
 
+       /* Always save/restore STH and TU registers in S0ix entry/exit */
+       scratchpad |= SCRPD_STH_IS_ENABLED | SCRPD_TRIGGER_IS_ENABLED;
+       iowrite32(scratchpad, gth->base + REG_GTH_SCRPD0);
+
        /* output ports */
        for (port = 0; port < 8; port++) {
                if (gth_output_parm_get(gth, port, TH_OUTPUT_PARM(port)) ==
@@ -488,6 +492,10 @@ static void intel_th_gth_disable(struct intel_th_device *thdev,
        if (!count)
                dev_dbg(&thdev->dev, "timeout waiting for GTH[%d] PLE\n",
                        output->port);
+
+       reg = ioread32(gth->base + REG_GTH_SCRPD0);
+       reg &= ~output->scratchpad;
+       iowrite32(reg, gth->base + REG_GTH_SCRPD0);
 }
 
 /**
@@ -502,7 +510,7 @@ static void intel_th_gth_enable(struct intel_th_device *thdev,
                                struct intel_th_output *output)
 {
        struct gth_device *gth = dev_get_drvdata(&thdev->dev);
-       u32 scr = 0xfc0000;
+       u32 scr = 0xfc0000, scrpd;
        int master;
 
        spin_lock(&gth->gth_lock);
@@ -517,6 +525,10 @@ static void intel_th_gth_enable(struct intel_th_device *thdev,
        output->active = true;
        spin_unlock(&gth->gth_lock);
 
+       scrpd = ioread32(gth->base + REG_GTH_SCRPD0);
+       scrpd |= output->scratchpad;
+       iowrite32(scrpd, gth->base + REG_GTH_SCRPD0);
+
        iowrite32(scr, gth->base + REG_GTH_SCR);
        iowrite32(0, gth->base + REG_GTH_SCR2);
 }

diff --git a/drivers/hwtracing/intel_th/gth.h b/drivers/hwtracing/intel_th/gth.h
index 3b714b7a61dbc1d614c7ad66917d6fd8af5e3319..56f0d2620577ca48f6b8b66e5cbf96a28e8b9318 100644 (file)
--- a/drivers/hwtracing/intel_th/gth.h
+++ b/drivers/hwtracing/intel_th/gth.h
@@ -57,9 +57,6 @@ enum {
        REG_GTH_SCRPD3          = 0xec, /* ScratchPad[3] */
 };
 
-/* Externall debugger is using Intel TH */
-#define SCRPD_DEBUGGER_IN_USE  BIT(24)
-
 /* waiting for Pipeline Empty bit(s) to assert for GTH */
 #define GTH_PLE_WAITLOOP_DEPTH 10000
 

diff --git a/drivers/hwtracing/intel_th/intel_th.h b/drivers/hwtracing/intel_th/intel_th.h
index 57fd72b20fae3135aa599475ce91e113abc4147d..eedd09332db6caf2eec08cfe69f2e1ac1160319a 100644 (file)
--- a/drivers/hwtracing/intel_th/intel_th.h
+++ b/drivers/hwtracing/intel_th/intel_th.h
@@ -30,6 +30,7 @@ enum {
  * struct intel_th_output - descriptor INTEL_TH_OUTPUT type devices
  * @port:      output port number, assigned by the switch
  * @type:      GTH_{MSU,CTP,PTI}
+ * @scratchpad:        scratchpad bits to flag when this output is enabled
  * @multiblock:        true for multiblock output configuration
  * @active:    true when this output is enabled
  *
@@ -41,6 +42,7 @@ enum {
 struct intel_th_output {
        int             port;
        unsigned int    type;
+       unsigned int    scratchpad;
        bool            multiblock;
        bool            active;
 };
@@ -241,4 +243,43 @@ enum {
        GTH_PTI = 4,    /* MIPI-PTI */
 };
 
+/*
+ * Scratchpad bits: tell firmware and external debuggers
+ * what we are up to.
+ */
+enum {
+       /* Memory is the primary destination */
+       SCRPD_MEM_IS_PRIM_DEST          = BIT(0),
+       /* XHCI DbC is the primary destination */
+       SCRPD_DBC_IS_PRIM_DEST          = BIT(1),
+       /* PTI is the primary destination */
+       SCRPD_PTI_IS_PRIM_DEST          = BIT(2),
+       /* BSSB is the primary destination */
+       SCRPD_BSSB_IS_PRIM_DEST         = BIT(3),
+       /* PTI is the alternate destination */
+       SCRPD_PTI_IS_ALT_DEST           = BIT(4),
+       /* BSSB is the alternate destination */
+       SCRPD_BSSB_IS_ALT_DEST          = BIT(5),
+       /* DeepSx exit occurred */
+       SCRPD_DEEPSX_EXIT               = BIT(6),
+       /* S4 exit occurred */
+       SCRPD_S4_EXIT                   = BIT(7),
+       /* S5 exit occurred */
+       SCRPD_S5_EXIT                   = BIT(8),
+       /* MSU controller 0/1 is enabled */
+       SCRPD_MSC0_IS_ENABLED           = BIT(9),
+       SCRPD_MSC1_IS_ENABLED           = BIT(10),
+       /* Sx exit occurred */
+       SCRPD_SX_EXIT                   = BIT(11),
+       /* Trigger Unit is enabled */
+       SCRPD_TRIGGER_IS_ENABLED        = BIT(12),
+       SCRPD_ODLA_IS_ENABLED           = BIT(13),
+       SCRPD_SOCHAP_IS_ENABLED         = BIT(14),
+       SCRPD_STH_IS_ENABLED            = BIT(15),
+       SCRPD_DCIH_IS_ENABLED           = BIT(16),
+       SCRPD_VER_IS_ENABLED            = BIT(17),
+       /* External debugger is using Intel TH */
+       SCRPD_DEBUGGER_IN_USE           = BIT(24),
+};
+
 #endif