*/
 void r100_pll_errata_after_index(struct radeon_device *rdev)
 {
-       if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
-               return;
+       if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
+               (void)RREG32(RADEON_CLOCK_CNTL_DATA);
+               (void)RREG32(RADEON_CRTC_GEN_CNTL);
        }
-       (void)RREG32(RADEON_CLOCK_CNTL_DATA);
-       (void)RREG32(RADEON_CRTC_GEN_CNTL);
 }
 
 static void r100_pll_errata_after_data(struct radeon_device *rdev)
 
                if (rev < 3) {
                        mem_cntl = RBIOS32(offset + 1);
                        mem_size = RBIOS16(offset + 5);
-                       if (((rdev->flags & RADEON_FAMILY_MASK) < CHIP_R200) &&
-                           ((dev->pdev->device != 0x515e)
-                            && (dev->pdev->device != 0x5969)))
+                       if ((rdev->family < CHIP_R200) &&
+                           !ASIC_IS_RN50(rdev))
                                WREG32(RADEON_MEM_CNTL, mem_cntl);
                }
        }
                if (offset) {
                        rev = RBIOS8(offset - 1);
                        if (rev < 1) {
-                               if (((rdev->flags & RADEON_FAMILY_MASK) <
-                                    CHIP_R200)
-                                   && ((dev->pdev->device != 0x515e)
-                                       && (dev->pdev->device != 0x5969))) {
+                               if ((rdev->family < CHIP_R200)
+                                   && !ASIC_IS_RN50(rdev)) {
                                        int ram = 0;
                                        int mem_addr_mapping = 0;