igc: add DCTL prefix to related macros

Rename macros to use the DCTL prefix for consistency with existing
macros that reference the same register. This prepares for an upcoming
patch that adds new fields to TXDCTL.

Reviewed-by: Simon Horman <horms@kernel.org>
Signed-off-by: Faizal Rahim <faizal.abdul.rahim@linux.intel.com>
Tested-by: Mor Bar-Gabay <morx.bar.gabay@intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>

diff --git a/drivers/net/ethernet/intel/igc/igc.h b/drivers/net/ethernet/intel/igc/igc.h
index 25695eada5633cd7871085f37cf2e6f92666ffda..db1e2db1619eb4965850cfae7560278a382a4955 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc.h
+++ b/drivers/net/ethernet/intel/igc/igc.h
@@ -485,17 +485,17 @@ static inline u32 igc_rss_type(const union igc_adv_rx_desc *rx_desc)
  *           descriptors until either it has this many to write back, or the
  *           ITR timer expires.
  */
-#define IGC_RX_PTHRESH                 8
-#define IGC_RX_HTHRESH                 8
-#define IGC_RX_WTHRESH                 4
+#define IGC_RXDCTL_PTHRESH             8
+#define IGC_RXDCTL_HTHRESH             8
+#define IGC_RXDCTL_WTHRESH             4
 /* Ena specific Rx Queue */
 #define IGC_RXDCTL_QUEUE_ENABLE                0x02000000
 /* Receive Software Flush */
 #define IGC_RXDCTL_SWFLUSH             0x04000000
 
-#define IGC_TX_PTHRESH                 8
-#define IGC_TX_HTHRESH                 1
-#define IGC_TX_WTHRESH                 16
+#define IGC_TXDCTL_PTHRESH             8
+#define IGC_TXDCTL_HTHRESH             1
+#define IGC_TXDCTL_WTHRESH             16
 /* Ena specific Tx Queue */
 #define IGC_TXDCTL_QUEUE_ENABLE                0x02000000
 /* Transmit Software Flush */

diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c
index 27575a1e1777fae67348499acdc36b8227e742cc..4f1a8bc006c619e852cfd93be5fcae9e58253637 100644 (file)
--- a/drivers/net/ethernet/intel/igc/igc_main.c
+++ b/drivers/net/ethernet/intel/igc/igc_main.c
@@ -683,9 +683,9 @@ static void igc_configure_rx_ring(struct igc_adapter *adapter,
 
        wr32(IGC_SRRCTL(reg_idx), srrctl);
 
-       rxdctl |= IGC_RX_PTHRESH;
-       rxdctl |= IGC_RX_HTHRESH << 8;
-       rxdctl |= IGC_RX_WTHRESH << 16;
+       rxdctl |= IGC_RXDCTL_PTHRESH;
+       rxdctl |= IGC_RXDCTL_HTHRESH << 8;
+       rxdctl |= IGC_RXDCTL_WTHRESH << 16;
 
        /* initialize rx_buffer_info */
        memset(ring->rx_buffer_info, 0,
@@ -749,9 +749,9 @@ static void igc_configure_tx_ring(struct igc_adapter *adapter,
        wr32(IGC_TDH(reg_idx), 0);
        writel(0, ring->tail);
 
-       txdctl |= IGC_TX_PTHRESH;
-       txdctl |= IGC_TX_HTHRESH << 8;
-       txdctl |= IGC_TX_WTHRESH << 16;
+       txdctl |= IGC_TXDCTL_PTHRESH;
+       txdctl |= IGC_TXDCTL_HTHRESH << 8;
+       txdctl |= IGC_TXDCTL_WTHRESH << 16;
 
        txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
        wr32(IGC_TXDCTL(reg_idx), txdctl);