#include <linux/module.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/power_supply.h>
 #include "pmf.h"
 
 /* PMF-SMU communication registers */
 #define DELAY_MIN_US   2000
 #define DELAY_MAX_US   3000
 
+int amd_pmf_get_power_source(void)
+{
+       if (power_supply_is_system_supplied() > 0)
+               return POWER_SOURCE_AC;
+       else
+               return POWER_SOURCE_DC;
+}
+
 static inline u32 amd_pmf_reg_read(struct amd_pmf_dev *dev, int reg_offset)
 {
        return ioread32(dev->regbase + reg_offset);
        { }
 };
 
+static void amd_pmf_init_features(struct amd_pmf_dev *dev)
+{
+       /* Enable Static Slider */
+       if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR)) {
+               amd_pmf_init_sps(dev);
+               dev_dbg(dev->dev, "SPS enabled and Platform Profiles registered\n");
+       }
+}
+
+static void amd_pmf_deinit_features(struct amd_pmf_dev *dev)
+{
+       if (is_apmf_func_supported(dev, APMF_FUNC_STATIC_SLIDER_GRANULAR))
+               amd_pmf_deinit_sps(dev);
+}
+
 static const struct acpi_device_id amd_pmf_acpi_ids[] = {
        {"AMDI0102", 0},
        { }
 
        apmf_acpi_init(dev);
        platform_set_drvdata(pdev, dev);
+       amd_pmf_init_features(dev);
 
        mutex_init(&dev->lock);
        dev_info(dev->dev, "registered PMF device successfully\n");
        struct amd_pmf_dev *dev = platform_get_drvdata(pdev);
 
        mutex_destroy(&dev->lock);
+       amd_pmf_deinit_features(dev);
        kfree(dev->buf);
        return 0;
 }
 
 #define PMF_H
 
 #include <linux/acpi.h>
+#include <linux/platform_profile.h>
 
 /* APMF Functions */
 #define APMF_FUNC_VERIFY_INTERFACE                     0
 #define APMF_FUNC_GET_SYS_PARAMS                       1
+#define APMF_FUNC_STATIC_SLIDER_GRANULAR       9
 
 /* Message Definitions */
 #define SET_SPL                                0x03 /* SPL: Sustained Power Limit */
 #define GET_STT_LIMIT_APU      0x20
 #define GET_STT_LIMIT_HS2      0x21
 
+#define ARG_NONE 0
+
 /* AMD PMF BIOS interfaces */
 struct apmf_verify_interface {
        u16 size;
        u8 command_code;
 } __packed;
 
+enum amd_stt_skin_temp {
+       STT_TEMP_APU,
+       STT_TEMP_HS2,
+       STT_TEMP_COUNT,
+};
+
+enum amd_slider_op {
+       SLIDER_OP_GET,
+       SLIDER_OP_SET,
+};
+
+enum power_source {
+       POWER_SOURCE_AC,
+       POWER_SOURCE_DC,
+       POWER_SOURCE_MAX,
+};
+
+enum power_modes {
+       POWER_MODE_PERFORMANCE,
+       POWER_MODE_BALANCED_POWER,
+       POWER_MODE_POWER_SAVER,
+       POWER_MODE_MAX,
+};
+
 struct amd_pmf_dev {
        void __iomem *regbase;
        void __iomem *smu_virt_addr;
        struct device *dev;
        struct mutex lock; /* protects the PMF interface */
        u32 supported_func;
+       enum platform_profile_option current_profile;
+       struct platform_profile_handler pprof;
+};
+
+struct apmf_sps_prop_granular {
+       u32 fppt;
+       u32 sppt;
+       u32 sppt_apu_only;
+       u32 spl;
+       u32 stt_min;
+       u8 stt_skin_temp[STT_TEMP_COUNT];
+       u32 fan_id;
+} __packed;
+
+/* Static Slider */
+struct apmf_static_slider_granular_output {
+       u16 size;
+       struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX];
+} __packed;
+
+struct amd_pmf_static_slider_granular {
+       u16 size;
+       struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX];
 };
 
 /* Core Layer */
 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev);
+int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index);
 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data);
+int amd_pmf_get_power_source(void);
+
+/* SPS Layer */
+u8 amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf);
+void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
+                          struct amd_pmf_static_slider_granular *table);
+int amd_pmf_init_sps(struct amd_pmf_dev *dev);
+void amd_pmf_deinit_sps(struct amd_pmf_dev *dev);
+int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev,
+                                   struct apmf_static_slider_granular_output *output);
+
 
 #endif /* PMF_H */
 
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * AMD Platform Management Framework (PMF) Driver
+ *
+ * Copyright (c) 2022, Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
+ */
+
+#include "pmf.h"
+
+static struct amd_pmf_static_slider_granular config_store;
+
+static void amd_pmf_load_defaults_sps(struct amd_pmf_dev *dev)
+{
+       struct apmf_static_slider_granular_output output;
+       int i, j, idx = 0;
+
+       memset(&config_store, 0, sizeof(config_store));
+       apmf_get_static_slider_granular(dev, &output);
+
+       for (i = 0; i < POWER_SOURCE_MAX; i++) {
+               for (j = 0; j < POWER_MODE_MAX; j++) {
+                       config_store.prop[i][j].spl = output.prop[idx].spl;
+                       config_store.prop[i][j].sppt = output.prop[idx].sppt;
+                       config_store.prop[i][j].sppt_apu_only =
+                                               output.prop[idx].sppt_apu_only;
+                       config_store.prop[i][j].fppt = output.prop[idx].fppt;
+                       config_store.prop[i][j].stt_min = output.prop[idx].stt_min;
+                       config_store.prop[i][j].stt_skin_temp[STT_TEMP_APU] =
+                                       output.prop[idx].stt_skin_temp[STT_TEMP_APU];
+                       config_store.prop[i][j].stt_skin_temp[STT_TEMP_HS2] =
+                                       output.prop[idx].stt_skin_temp[STT_TEMP_HS2];
+                       config_store.prop[i][j].fan_id = output.prop[idx].fan_id;
+                       idx++;
+               }
+       }
+}
+
+void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx,
+                          struct amd_pmf_static_slider_granular *table)
+{
+       int src = amd_pmf_get_power_source();
+
+       if (op == SLIDER_OP_SET) {
+               amd_pmf_send_cmd(dev, SET_SPL, false, config_store.prop[src][idx].spl, NULL);
+               amd_pmf_send_cmd(dev, SET_FPPT, false, config_store.prop[src][idx].fppt, NULL);
+               amd_pmf_send_cmd(dev, SET_SPPT, false, config_store.prop[src][idx].sppt, NULL);
+               amd_pmf_send_cmd(dev, SET_SPPT_APU_ONLY, false,
+                                config_store.prop[src][idx].sppt_apu_only, NULL);
+               amd_pmf_send_cmd(dev, SET_STT_MIN_LIMIT, false,
+                                config_store.prop[src][idx].stt_min, NULL);
+               amd_pmf_send_cmd(dev, SET_STT_LIMIT_APU, false,
+                                config_store.prop[src][idx].stt_skin_temp[STT_TEMP_APU], NULL);
+               amd_pmf_send_cmd(dev, SET_STT_LIMIT_HS2, false,
+                                config_store.prop[src][idx].stt_skin_temp[STT_TEMP_HS2], NULL);
+       } else if (op == SLIDER_OP_GET) {
+               amd_pmf_send_cmd(dev, GET_SPL, true, ARG_NONE, &table->prop[src][idx].spl);
+               amd_pmf_send_cmd(dev, GET_FPPT, true, ARG_NONE, &table->prop[src][idx].fppt);
+               amd_pmf_send_cmd(dev, GET_SPPT, true, ARG_NONE, &table->prop[src][idx].sppt);
+               amd_pmf_send_cmd(dev, GET_SPPT_APU_ONLY, true, ARG_NONE,
+                                &table->prop[src][idx].sppt_apu_only);
+               amd_pmf_send_cmd(dev, GET_STT_MIN_LIMIT, true, ARG_NONE,
+                                &table->prop[src][idx].stt_min);
+               amd_pmf_send_cmd(dev, GET_STT_LIMIT_APU, true, ARG_NONE,
+                                (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_APU]);
+               amd_pmf_send_cmd(dev, GET_STT_LIMIT_HS2, true, ARG_NONE,
+                                (u32 *)&table->prop[src][idx].stt_skin_temp[STT_TEMP_HS2]);
+       }
+}
+
+static int amd_pmf_profile_get(struct platform_profile_handler *pprof,
+                              enum platform_profile_option *profile)
+{
+       struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof);
+
+       *profile = pmf->current_profile;
+       return 0;
+}
+
+u8 amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf)
+{
+       u8 mode;
+
+       switch (pmf->current_profile) {
+       case PLATFORM_PROFILE_PERFORMANCE:
+               mode = POWER_MODE_PERFORMANCE;
+               break;
+       case PLATFORM_PROFILE_BALANCED:
+               mode = POWER_MODE_BALANCED_POWER;
+               break;
+       case PLATFORM_PROFILE_LOW_POWER:
+               mode = POWER_MODE_POWER_SAVER;
+               break;
+       default:
+               dev_err(pmf->dev, "Unknown Platform Profile.\n");
+               break;
+       }
+
+       return mode;
+}
+
+static int amd_pmf_profile_set(struct platform_profile_handler *pprof,
+                              enum platform_profile_option profile)
+{
+       struct amd_pmf_dev *pmf = container_of(pprof, struct amd_pmf_dev, pprof);
+       u8 mode;
+
+       pmf->current_profile = profile;
+       mode = amd_pmf_get_pprof_modes(pmf);
+       amd_pmf_update_slider(pmf, SLIDER_OP_SET, mode, NULL);
+       return 0;
+}
+
+int amd_pmf_init_sps(struct amd_pmf_dev *dev)
+{
+       int err;
+
+       dev->current_profile = PLATFORM_PROFILE_BALANCED;
+       amd_pmf_load_defaults_sps(dev);
+
+       dev->pprof.profile_get = amd_pmf_profile_get;
+       dev->pprof.profile_set = amd_pmf_profile_set;
+
+       /* Setup supported modes */
+       set_bit(PLATFORM_PROFILE_LOW_POWER, dev->pprof.choices);
+       set_bit(PLATFORM_PROFILE_BALANCED, dev->pprof.choices);
+       set_bit(PLATFORM_PROFILE_PERFORMANCE, dev->pprof.choices);
+
+       /* Create platform_profile structure and register */
+       err = platform_profile_register(&dev->pprof);
+       if (err)
+               dev_err(dev->dev, "Failed to register SPS support, this is most likely an SBIOS bug: %d\n",
+                       err);
+
+       return err;
+}
+
+void amd_pmf_deinit_sps(struct amd_pmf_dev *dev)
+{
+       platform_profile_remove();
+}