clk: renesas: r8a779a0: Use defines for PLL control registers

Add symbolic definitions for the various PLL control registers.
Replace hardcoded register offsets by the new definitions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/8cac464c7dfb15ecd299b8ab4ba88a16135f8123.1721648548.git.geert+renesas@glider.be

diff --git a/drivers/clk/renesas/r8a779a0-cpg-mssr.c b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
index 14042d6dc4dd3e21c704e6377de6b51fabe7a60d..e6e2c3c16c8d5befa7cdd701b37da30cab18d234 100644 (file)
--- a/drivers/clk/renesas/r8a779a0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779a0-cpg-mssr.c
@@ -61,6 +61,11 @@ enum clk_ids {
        DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL2X_3X, CLK_MAIN, \
                 .offset = _offset)
 
+#define CPG_PLL20CR    0x0834  /* PLL20 Control Register */
+#define CPG_PLL21CR    0x0838  /* PLL21 Control Register */
+#define CPG_PLL30CR    0x083c  /* PLL30 Control Register */
+#define CPG_PLL31CR    0x0840  /* PLL31 Control Register */
+
 static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        /* External Clock Inputs */
        DEF_INPUT("extal",  CLK_EXTAL),
@@ -70,10 +75,10 @@ static const struct cpg_core_clk r8a779a0_core_clks[] __initconst = {
        DEF_BASE(".main", CLK_MAIN,     CLK_TYPE_GEN4_MAIN, CLK_EXTAL),
        DEF_BASE(".pll1", CLK_PLL1,     CLK_TYPE_GEN4_PLL1, CLK_MAIN),
        DEF_BASE(".pll5", CLK_PLL5,     CLK_TYPE_GEN4_PLL5, CLK_MAIN),
-       DEF_PLL(".pll20", CLK_PLL20,    0x0834),
-       DEF_PLL(".pll21", CLK_PLL21,    0x0838),
-       DEF_PLL(".pll30", CLK_PLL30,    0x083c),
-       DEF_PLL(".pll31", CLK_PLL31,    0x0840),
+       DEF_PLL(".pll20", CLK_PLL20,    CPG_PLL20CR),
+       DEF_PLL(".pll21", CLK_PLL21,    CPG_PLL21CR),
+       DEF_PLL(".pll30", CLK_PLL30,    CPG_PLL30CR),
+       DEF_PLL(".pll31", CLK_PLL31,    CPG_PLL31CR),
 
        DEF_FIXED(".pll1_div2",         CLK_PLL1_DIV2,  CLK_PLL1,       2, 1),
        DEF_FIXED(".pll20_div2",        CLK_PLL20_DIV2, CLK_PLL20,      2, 1),