compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-                                <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
+                                <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
-                               R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
+                               R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
+                               R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
                        >;
                        clock-output-names =
                                "tpu0", "sdhi2", "sdhi1", "sdhi0",
-                               "mmcif0", "i2c7", "i2c8", "ssusb", "cmt1";
+                               "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
 
 #define R8A7791_CLK_SDHI0              14
 #define R8A7791_CLK_MMCIF0             15
 #define R8A7791_CLK_IIC0               18
+#define R8A7791_CLK_PCIEC              19
 #define R8A7791_CLK_IIC1               23
 #define R8A7791_CLK_SSUSB              28
 #define R8A7791_CLK_CMT1               29