drm/i915: Rename QGV request/response bits

Name all the ICL_PCODE_SAGV_DE_MEM_SS_CONFIG request/response
bits in a manner that we can actually understand what they're
doing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220309164948.10671-9-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b794545ff81db17f99d48a79625139e7994cb7a2..395e48930b08901c136c1027cd0b975030c671f8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -124,8 +124,8 @@ int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
        /* bspec says to keep retrying for at least 1 ms */
        ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
                                points_mask,
-                               ICL_PCODE_POINTS_RESTRICTED_MASK,
-                               ICL_PCODE_POINTS_RESTRICTED,
+                               ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
+                               ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
                                1);
 
        if (ret < 0) {
@@ -833,7 +833,7 @@ static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
        if (num_psf_gv_points > 0)
                psf_points = GENMASK(num_psf_gv_points - 1, 0);
 
-       return ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points);
+       return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
 }
 
 static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
@@ -1000,7 +1000,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
         * actually accepts as a parameter.
         */
        new_bw_state->qgv_points_mask =
-               ~(ADLS_QGV_PT(qgv_points) | ADLS_PSF_PT(psf_points)) &
+               ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
+                 ADLS_PCODE_REQ_PSF_PT(psf_points)) &
                icl_qgv_points_mask(dev_priv);
 
        /*

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac6b5c74128933ba3cd1096e031e3c7356ba877d..77c6f259eda1ee7c84d124fb6911c8dcba4f2059 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6718,12 +6718,18 @@
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)        (((point) << 16) | (0x1 << 8))
 #define     ADL_PCODE_MEM_SS_READ_PSF_GV_INFO  ((0) | (0x2 << 8))
 #define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG      0xe
-#define     ICL_PCODE_POINTS_RESTRICTED                0x0
-#define     ICL_PCODE_POINTS_RESTRICTED_MASK   0xf
-#define   ADLS_QGV_PT_MASK                     REG_GENMASK(7, 0)
-#define   ADLS_QGV_PT(x)                       REG_FIELD_PREP(ADLS_QGV_PT_MASK, (x))
-#define   ADLS_PSF_PT_MASK                     REG_GENMASK(10, 8)
-#define   ADLS_PSF_PT(x)                       REG_FIELD_PREP(ADLS_PSF_PT_MASK, (x))
+#define     ICL_PCODE_REP_QGV_MASK             REG_GENMASK(1, 0)
+#define     ICL_PCODE_REP_QGV_SAFE             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define     ICL_PCODE_REP_QGV_POLL             REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define     ICL_PCODE_REP_QGV_REJECTED         REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define     ADLS_PCODE_REP_PSF_MASK            REG_GENMASK(3, 2)
+#define     ADLS_PCODE_REP_PSF_SAFE            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define     ADLS_PCODE_REP_PSF_POLL            REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define     ADLS_PCODE_REP_PSF_REJECTED                REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define     ICL_PCODE_REQ_QGV_PT_MASK          REG_GENMASK(7, 0)
+#define     ICL_PCODE_REQ_QGV_PT(x)            REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define     ADLS_PCODE_REQ_PSF_PT_MASK         REG_GENMASK(10, 8)
+#define     ADLS_PCODE_REQ_PSF_PT(x)           REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
 #define   GEN6_PCODE_READ_D_COMP               0x10
 #define   GEN6_PCODE_WRITE_D_COMP              0x11
 #define   ICL_PCODE_EXIT_TCCOLD                        0x12