#define SUN4V_CHIP_SPARC_M7 0x07
#define SUN4V_CHIP_SPARC_M8 0X08
#define SUN4V_CHIP_SPARC_S7 0x7a
+#define SUN4V_CHIP_SPARC_S8 0x7b
#define SUN4V_CHIP_SPARC64X 0x8a
#define SUN4V_CHIP_UNKNOWN 0xff
sparc_pmu_type = "sparc-s7";
break;
+ case SUN4V_CHIP_SPARC_S8:
+ sparc_cpu_type = "SPARC-S8 (Sonoma2)";
+ sparc_fpu_type = "SPARC-S8 integrated FPU";
+ sparc_pmu_type = "sparc-s8";
+ break;
+
case SUN4V_CHIP_SPARC64X:
sparc_cpu_type = "SPARC64-X";
sparc_fpu_type = "SPARC64-X integrated FPU";
cmp %g2, '7'
be,pt %xcc, 5f
mov SUN4V_CHIP_SPARC_S7, %g4
+ cmp %g2, '8'
+ be,pt %xcc, 5f
+ mov SUN4V_CHIP_SPARC_S8, %g4
ba,pt %xcc, 49f
nop
91: sethi %hi(prom_cpu_compatible), %g1