clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

The PCIe PIPE clock in the GCC is fed by the PIPE clock coming from the
PHY, describe this relationship.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/gcc-sdm845.c b/drivers/clk/qcom/gcc-sdm845.c
index c782e62dd98b8949e469cc3c0ca12eb288d0f58f..83843896177d80380a829e30ae57e5983a75b1b0 100644 (file)
--- a/drivers/clk/qcom/gcc-sdm845.c
+++ b/drivers/clk/qcom/gcc-sdm845.c
@@ -1697,6 +1697,9 @@ static struct clk_branch gcc_pcie_0_pipe_clk = {
                .enable_mask = BIT(4),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_0_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_0_pipe_clk" },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
                        .ops = &clk_branch2_ops,
                },
        },
@@ -1796,6 +1799,8 @@ static struct clk_branch gcc_pcie_1_pipe_clk = {
                .enable_mask = BIT(30),
                .hw.init = &(struct clk_init_data){
                        .name = "gcc_pcie_1_pipe_clk",
+                       .parent_names = (const char *[]){ "pcie_1_pipe_clk" },
+                       .num_parents = 1,
                        .ops = &clk_branch2_ops,
                },
        },