return -EINVAL;
        }
 
-       if (pwm->period != period_ns) {
+       if (pwm_get_period(pwm) != period_ns) {
                int clk_div;
 
                /* changing the clk divisor, need to disable fisrt */
 
                           LPC18XX_PWM_EVSTATEMSK(lpc18xx_data->duty_event),
                           LPC18XX_PWM_EVSTATEMSK_ALL);
 
-       if (pwm->polarity == PWM_POLARITY_NORMAL) {
+       if (pwm_get_polarity(pwm) == PWM_POLARITY_NORMAL) {
                set_event = lpc18xx_pwm->period_event;
                clear_event = lpc18xx_data->duty_event;
                res_action = LPC18XX_PWM_RES_SET;
 
                load_value, load_value, match_value, match_value);
 
        omap->pdata->set_pwm(omap->dm_timer,
-                             pwm->polarity == PWM_POLARITY_INVERSED,
+                             pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
                              true,
                              PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
 
 
        val = sun4i_pwm_readl(pwm, PWM_CTRL_REG);
        for (i = 0; i < pwm->chip.npwm; i++)
                if (!(val & BIT_CH(PWM_ACT_STATE, i)))
-                       pwm->chip.pwms[i].polarity = PWM_POLARITY_INVERSED;
+                       pwm_set_polarity(&pwm->chip.pwms[i],
+                                        PWM_POLARITY_INVERSED);
        clk_disable_unprepare(pwm->clk);
 
        return 0;