scsi: hisi_sas: Modify macro name for OOB phy linkrate

The macro for OOB phy linkrate is named CFG_PROG_PHY_LINK_RATE_* but that
is inaccurate. For clarification, include OOB in macro name.

Link: https://lore.kernel.org/r/1598958790-232272-3-git-send-email-john.garry@huawei.com
Signed-off-by: Luo Jiaxing <luojiaxing@huawei.com>
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index 60adf5c32143d2c373821857dd0edbe0bc589a72..05b60cdf6b24880147cf1534dc9d70926b7b0745 100644 (file)
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -191,8 +191,8 @@
 #define PHY_CFG_PHY_RST_OFF            3
 #define PHY_CFG_PHY_RST_MSK            (0x1 << PHY_CFG_PHY_RST_OFF)
 #define PROG_PHY_LINK_RATE             (PORT_BASE + 0x8)
-#define CFG_PROG_PHY_LINK_RATE_OFF     8
-#define CFG_PROG_PHY_LINK_RATE_MSK     (0xf << CFG_PROG_PHY_LINK_RATE_OFF)
+#define CFG_PROG_OOB_PHY_LINK_RATE_OFF 8
+#define CFG_PROG_OOB_PHY_LINK_RATE_MSK (0xf << CFG_PROG_OOB_PHY_LINK_RATE_OFF)
 #define PHY_CTRL                       (PORT_BASE + 0x14)
 #define PHY_CTRL_RESET_OFF             0
 #define PHY_CTRL_RESET_MSK             (0x1 << PHY_CTRL_RESET_OFF)
@@ -2998,8 +2998,8 @@ static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba)
        /* restore the linkrate */
        reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, PROG_PHY_LINK_RATE);
        /* init OOB link rate as 1.5 Gbits */
-       reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK;
-       reg_val |= (0x8 << CFG_PROG_PHY_LINK_RATE_OFF);
+       reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
+       reg_val |= (0x8 << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
        hisi_sas_phy_write32(hisi_hba, phy_id, PROG_PHY_LINK_RATE, reg_val);
 
        /* enable PHY */
@@ -3027,8 +3027,8 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
                /* set linkrate of bit test*/
                reg_val = hisi_sas_phy_read32(hisi_hba, phy_id,
                                              PROG_PHY_LINK_RATE);
-               reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK;
-               reg_val |= (linkrate << CFG_PROG_PHY_LINK_RATE_OFF);
+               reg_val &= ~CFG_PROG_OOB_PHY_LINK_RATE_MSK;
+               reg_val |= (linkrate << CFG_PROG_OOB_PHY_LINK_RATE_OFF);
                hisi_sas_phy_write32(hisi_hba, phy_id,
                                     PROG_PHY_LINK_RATE, reg_val);
 
@@ -3050,8 +3050,7 @@ static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable)
                hisi_sas_phy_write32(hisi_hba, phy_id,
                                     SAS_PHY_BIST_CODE,
                                     SAS_PHY_BIST_CODE_INIT);
-               hisi_sas_phy_write32(hisi_hba, phy_id,
-                                    SAS_PHY_BIST_CODE1,
+               hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CODE1,
                                     SAS_PHY_BIST_CODE1_INIT);
 
                mdelay(100);