arm64: dts: renesas: r9a07g044: Add DU node

Add DU node to RZ/G2L SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240222132117.137729-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
index 081d8f49db879773bd263287f5ae6a53863e4083..086169d5a83d8270087b9ebe686e1de816cf649f 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi
@@ -820,6 +820,33 @@
                        resets = <&cpg R9A07G044_LCDC_RESET_N>;
                };
 
+               du: display@10890000 {
+                       compatible = "renesas,r9a07g044-du";
+                       reg = <0 0x10890000 0 0x10000>;
+                       interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
+                                <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
+                                <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg R9A07G044_LCDC_RESET_N>;
+                       renesas,vsps = <&vspd 0>;
+                       status = "disabled";
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+                               };
+                       };
+               };
+
                cpg: clock-controller@11010000 {
                        compatible = "renesas,r9a07g044-cpg";
                        reg = <0 0x11010000 0 0x10000>;