int i;
 
        if (is_support_cclk_dpm(adev)) {
-               p_val = kcalloc(boot_cpu_data.x86_max_cores, sizeof(uint16_t),
+               p_val = kcalloc(adev->smu.cpu_core_num, sizeof(uint16_t),
                                GFP_KERNEL);
 
                if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_CPU_CLK,
                                            (void *)p_val, &size)) {
-                       for (i = 0; i < boot_cpu_data.x86_max_cores; i++)
+                       for (i = 0; i < adev->smu.cpu_core_num; i++)
                                seq_printf(m, "\t%u MHz (CPU%d)\n",
                                           *(p_val + i), i);
                }
 
        uint32_t gfx_actual_hard_min_freq;
        uint32_t gfx_actual_soft_max_freq;
 
+       /* APU only */
        uint32_t cpu_default_soft_min_freq;
        uint32_t cpu_default_soft_max_freq;
        uint32_t cpu_actual_soft_min_freq;
        uint32_t cpu_actual_soft_max_freq;
        uint32_t cpu_core_id_select;
+       uint16_t cpu_core_num;
 };
 
 struct i2c_adapter;
 
                break;
        case METRICS_AVERAGE_CPUCLK:
                memcpy(value, &metrics->CoreFrequency[0],
-                      boot_cpu_data.x86_max_cores * sizeof(uint16_t));
+                      smu->cpu_core_num * sizeof(uint16_t));
                break;
        default:
                *value = UINT_MAX;
        if (ret)
                return ret;
 
+#ifdef CONFIG_X86
+       /* AMD x86 APU only */
+       smu->cpu_core_num = boot_cpu_data.x86_max_cores;
+#else
+       smu->cpu_core_num = 4;
+#endif
+
        return smu_v11_0_init_smc_tables(smu);
 }
 
                ret = vangogh_get_smu_metrics_data(smu,
                                                   METRICS_AVERAGE_CPUCLK,
                                                   (uint32_t *)data);
-               *size = boot_cpu_data.x86_max_cores * sizeof(uint16_t);
+               *size = smu->cpu_core_num * sizeof(uint16_t);
                break;
        default:
                ret = -EOPNOTSUPP;
                        dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
                        return -EINVAL;
                }
-               if (input[0] >= boot_cpu_data.x86_max_cores) {
+               if (input[0] >= smu->cpu_core_num) {
                        dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
-                               boot_cpu_data.x86_max_cores);
+                               smu->cpu_core_num);
                }
                smu->cpu_core_id_select = input[0];
                if (input[1] == 0) {
                                break;
                        }
 
-                       for (i = 0; i < boot_cpu_data.x86_max_cores; i++) {
+                       for (i = 0; i < smu->cpu_core_num; i++) {
                                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
                                                                      (i << 20) | smu->cpu_actual_soft_min_freq,
                                                                      NULL);