net/mlx5e: Support FEC settings for 100G/lane modes

This consists of:
1. Expose the 100G/lane capability bit in the PCAM reg.
2. Expose the per link mode FEC capability masks in the PPLM reg.
3. Set the overrides according to ethtool parameters.
FEC for new modes is set if and only if the PCAM 100G/lane capability is
advertised and the capability mask for a given link mode reports that it
can accept the requested FEC mode.

Signed-off-by: Cosmin Ratiu <cratiu@nvidia.com>
Reviewed-by: Gal Pressman <gal@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
Link: https://lore.kernel.org/r/20240404173357.123307-3-tariqt@nvidia.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
index b4681a93807d3e599f6f601abf2326047b97f5ad..b4efc780e29707795d71efe9667c6d2c010015b8 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port.c
@@ -292,10 +292,15 @@ enum mlx5e_fec_supported_link_mode {
        MLX5E_FEC_SUPPORTED_LINK_MODE_100G_2X,
        MLX5E_FEC_SUPPORTED_LINK_MODE_200G_4X,
        MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X,
+       MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X,
+       MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X,
+       MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X,
+       MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X,
        MLX5E_MAX_FEC_SUPPORTED_LINK_MODE,
 };
 
 #define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X
+#define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X
 
 #define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link)                      \
        do {                                                                            \
@@ -313,7 +318,10 @@ static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev,
                                             enum mlx5e_fec_supported_link_mode link_mode)
 {
        return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE ||
-              MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
+              (link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
+               MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) ||
+              (link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&
+               MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm));
 }
 
 /* get/set FEC admin field for a given speed */
@@ -348,6 +356,18 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write,
        case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X:
                MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_8x);
                break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X:
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 100g_1x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X:
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_2x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X:
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_4x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
+               MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x);
+               break;
        default:
                return -EINVAL;
        }
@@ -389,6 +409,18 @@ static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap,
        case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_8X:
                *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_8x);
                break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X:
+               *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 100g_1x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X:
+               *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_2x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X:
+               *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_4x);
+               break;
+       case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:
+               *fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x);
+               break;
        default:
                return -EINVAL;
        }
@@ -501,7 +533,7 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)
                /* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514
                 * to link modes up to 25G per lane and to
                 * MLX5E_FEC_RS_544_514 in the new link modes based on
-                * 50 G per lane
+                * 50G or 100G per lane
                 */
                if (conf_fec == (1 << MLX5E_FEC_RS_528_514) &&
                    i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index cc159d8563d19ba9116a2127472597e2dbfbf554..35ffc9b9f24191284049acf3da51a5331987eafc 100644 (file)
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -9817,7 +9817,21 @@ struct mlx5_ifc_pplm_reg_bits {
        u8         fec_override_admin_100g_2x[0x10];
        u8         fec_override_admin_50g_1x[0x10];
 
-       u8         reserved_at_140[0x140];
+       u8         fec_override_cap_800g_8x[0x10];
+       u8         fec_override_cap_400g_4x[0x10];
+
+       u8         fec_override_cap_200g_2x[0x10];
+       u8         fec_override_cap_100g_1x[0x10];
+
+       u8         reserved_at_180[0xa0];
+
+       u8         fec_override_admin_800g_8x[0x10];
+       u8         fec_override_admin_400g_4x[0x10];
+
+       u8         fec_override_admin_200g_2x[0x10];
+       u8         fec_override_admin_100g_1x[0x10];
+
+       u8         reserved_at_260[0x20];
 };
 
 struct mlx5_ifc_ppcnt_reg_bits {
@@ -10189,7 +10203,9 @@ struct mlx5_ifc_mtutc_reg_bits {
 };
 
 struct mlx5_ifc_pcam_enhanced_features_bits {
-       u8         reserved_at_0[0x68];
+       u8         reserved_at_0[0x48];
+       u8         fec_100G_per_lane_in_pplm[0x1];
+       u8         reserved_at_49[0x1f];
        u8         fec_50G_per_lane_in_pplm[0x1];
        u8         reserved_at_69[0x4];
        u8         rx_icrc_encapsulated_counter[0x1];