drm/i915/tgl: Add HDC Pipeline Flush

Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.

v2: Flush also in breadcrumbs (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index afc869dc785fed2c5e6df77c7516a320e2ae64f6..4294f146f13c41131cef0e244f79efb2c62db793 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -235,6 +235,7 @@
 #define   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE                (1<<10) /* GM45+ only */
 #define   PIPE_CONTROL_L3_RO_CACHE_INVALIDATE          REG_BIT(10) /* gen12 */
 #define   PIPE_CONTROL_INDIRECT_STATE_DISABLE          (1<<9)
+#define   PIPE_CONTROL_HDC_PIPELINE_FLUSH              REG_BIT(9)  /* gen12 */
 #define   PIPE_CONTROL_NOTIFY                          (1<<8)
 #define   PIPE_CONTROL_FLUSH_ENABLE                    (1<<7) /* gen7+ */
 #define   PIPE_CONTROL_DC_FLUSH_ENABLE                 (1<<5)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 217f6513e117082d161764960ec28f45e06bf5aa..d1b10f00d72938c2d395524ab205e7a7e8ef66f4 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3205,6 +3205,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
                flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
                flags |= PIPE_CONTROL_FLUSH_ENABLE;
+               flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
 
                flags |= PIPE_CONTROL_STORE_DATA_INDEX;
                flags |= PIPE_CONTROL_QW_WRITE;
@@ -3415,7 +3416,8 @@ gen12_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs)
                                      PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH |
                                      PIPE_CONTROL_DEPTH_CACHE_FLUSH |
                                      PIPE_CONTROL_DC_FLUSH_ENABLE |
-                                     PIPE_CONTROL_FLUSH_ENABLE);
+                                     PIPE_CONTROL_FLUSH_ENABLE |
+                                     PIPE_CONTROL_HDC_PIPELINE_FLUSH);
 
        return gen12_emit_fini_breadcrumb_footer(request, cs);
 }