/* Further private data for which no space exists in mips_fpu_soft_struct */
 
-struct mips_fpu_emulator_private fpuemuprivate;
+struct mips_fpu_emulator_stats fpuemustats;
 
 /* Control registers */
 
        unsigned int cond;
 
        if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) {
-               fpuemuprivate.stats.errors++;
+               fpuemustats.errors++;
                return SIGBUS;
        }
 
                        return SIGILL;
                }
                if (get_user(ir, (mips_instruction *) emulpc)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
                /* __compute_return_epc() will have updated cp0_epc */
        }
 
       emul:
-       fpuemuprivate.stats.emulated++;
+       fpuemustats.emulated++;
        switch (MIPSInst_OPCODE(ir)) {
 #ifndef SINGLE_ONLY_FPU
        case ldc1_op:{
                        MIPSInst_SIMM(ir));
                u64 val;
 
-               fpuemuprivate.stats.loads++;
+               fpuemustats.loads++;
                if (get_user(val, va)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
                DITOREG(val, MIPSInst_RT(ir));
                        MIPSInst_SIMM(ir));
                u64 val;
 
-               fpuemuprivate.stats.stores++;
+               fpuemustats.stores++;
                DIFROMREG(val, MIPSInst_RT(ir));
                if (put_user(val, va)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
                break;
                        MIPSInst_SIMM(ir));
                u32 val;
 
-               fpuemuprivate.stats.loads++;
+               fpuemustats.loads++;
                if (get_user(val, va)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
 #ifdef SINGLE_ONLY_FPU
                        MIPSInst_SIMM(ir));
                u32 val;
 
-               fpuemuprivate.stats.stores++;
+               fpuemustats.stores++;
 #ifdef SINGLE_ONLY_FPU
                if (MIPSInst_RT(ir) & 1) {
                        /* illegal register in single-float mode */
 #endif
                SIFROMREG(val, MIPSInst_RT(ir));
                if (put_user(val, va)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
                break;
 
                                if (get_user(ir, (mips_instruction *)
                                                (void *)  xcp->cp0_epc)) {
-                                       fpuemuprivate.stats.errors++;
+                                       fpuemustats.errors++;
                                        return SIGBUS;
                                }
 
 {
        unsigned rcsr = 0;      /* resulting csr */
 
-       fpuemuprivate.stats.cp1xops++;
+       fpuemustats.cp1xops++;
 
        switch (MIPSInst_FMA_FFMT(ir)) {
        case s_fmt:{            /* 0 */
                        va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
                                xcp->regs[MIPSInst_FT(ir)]);
 
-                       fpuemuprivate.stats.loads++;
+                       fpuemustats.loads++;
                        if (get_user(val, va)) {
-                               fpuemuprivate.stats.errors++;
+                               fpuemustats.errors++;
                                return SIGBUS;
                        }
 #ifdef SINGLE_ONLY_FPU
                        va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
                                xcp->regs[MIPSInst_FT(ir)]);
 
-                       fpuemuprivate.stats.stores++;
+                       fpuemustats.stores++;
 #ifdef SINGLE_ONLY_FPU
                        if (MIPSInst_FS(ir) & 1) {
                                /* illegal register in single-float
 
                        SIFROMREG(val, MIPSInst_FS(ir));
                        if (put_user(val, va)) {
-                               fpuemuprivate.stats.errors++;
+                               fpuemustats.errors++;
                                return SIGBUS;
                        }
                        break;
                        va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
                                xcp->regs[MIPSInst_FT(ir)]);
 
-                       fpuemuprivate.stats.loads++;
+                       fpuemustats.loads++;
                        if (get_user(val, va)) {
-                               fpuemuprivate.stats.errors++;
+                               fpuemustats.errors++;
                                return SIGBUS;
                        }
                        DITOREG(val, MIPSInst_FD(ir));
                        va = (void *) (xcp->regs[MIPSInst_FR(ir)] +
                                xcp->regs[MIPSInst_FT(ir)]);
 
-                       fpuemuprivate.stats.stores++;
+                       fpuemustats.stores++;
                        DIFROMREG(val, MIPSInst_FS(ir));
                        if (put_user(val, va)) {
-                               fpuemuprivate.stats.errors++;
+                               fpuemustats.errors++;
                                return SIGBUS;
                        }
                        break;
 #endif
        } rv;                   /* resulting value */
 
-       fpuemuprivate.stats.cp1ops++;
+       fpuemustats.cp1ops++;
        switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
        case s_fmt:{            /* 0 */
                union {
                prevepc = xcp->cp0_epc;
 
                if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
-                       fpuemuprivate.stats.errors++;
+                       fpuemustats.errors++;
                        return SIGBUS;
                }
                if (insn == 0)