struct amdgpu_reset_control     *reset_cntl;
        uint32_t                        ip_versions[MAX_HWIP][HWIP_MAX_INSTANCE];
+
+       bool                            ram_is_direct_mapped;
 };
 
 static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev)
 
 #include <linux/module.h>
 #include <linux/console.h>
 #include <linux/slab.h>
+#include <linux/iommu.h>
 
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_probe_helper.h>
        return ret;
 }
 
+/**
+ * amdgpu_device_check_iommu_direct_map - check if RAM direct mapped to GPU
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * RAM direct mapped to GPU if IOMMU is not enabled or is pass through mode
+ */
+static void amdgpu_device_check_iommu_direct_map(struct amdgpu_device *adev)
+{
+       struct iommu_domain *domain;
+
+       domain = iommu_get_domain_for_dev(adev->dev);
+       if (!domain || domain->type == IOMMU_DOMAIN_IDENTITY)
+               adev->ram_is_direct_mapped = true;
+}
+
 static const struct attribute *amdgpu_dev_attributes[] = {
        &dev_attr_product_name.attr,
        &dev_attr_product_number.attr,
                queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work,
                                   msecs_to_jiffies(AMDGPU_RESUME_MS));
 
+       amdgpu_device_check_iommu_direct_map(adev);
+
        return 0;
 
 release_ras_con: