#define PCH_PP_STATUS          0xc7200
 #define PCH_PP_CONTROL         0xc7204
+#define  PANEL_UNLOCK_REGS     (0xabcd << 16)
 #define  EDP_FORCE_VDD         (1 << 3)
 #define  EDP_BLC_ENABLE                (1 << 2)
 #define  PANEL_POWER_RESET     (1 << 1)
 
                DRM_DEBUG_DRIVER("upclocking LVDS\n");
 
                /* Unlock panel regs */
-               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                          PANEL_UNLOCK_REGS);
 
                dpll &= ~DISPLAY_RATE_SELECT_FPA1;
                I915_WRITE(dpll_reg, dpll);
                DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                /* Unlock panel regs */
-               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+               I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                          PANEL_UNLOCK_REGS);
 
                dpll |= DISPLAY_RATE_SELECT_FPA1;
                I915_WRITE(dpll_reg, dpll);