void __init imx_init_revision_from_anatop(void)
 {
-       struct device_node *np;
+       struct device_node *np, *src_np;
        void __iomem *anatop_base;
        unsigned int revision;
        u32 digprog;
                        void __iomem *src_base;
                        u32 sbmr2;
 
-                       np = of_find_compatible_node(NULL, NULL,
+                       src_np = of_find_compatible_node(NULL, NULL,
                                                     "fsl,imx6ul-src");
                        src_base = of_iomap(np, 0);
+                       of_node_put(src_np);
                        WARN_ON(!src_base);
                        sbmr2 = readl_relaxed(src_base + SRC_SBMR2);
                        iounmap(src_base);
                        }
                }
        }
+       of_node_put(np);
 
        mxc_set_cpu_type(digprog >> 16 & 0xff);
        imx_set_soc_revision(revision);
 
                /* map GPC, so that at least CPUidle and WARs keep working */
                gpc_base = of_iomap(np, 0);
        }
+       of_node_put(np);
 }
 
 
        np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
        dcfg_base = of_iomap(np, 0);
+       of_node_put(np);
        BUG_ON(!dcfg_base);
 
        paddr = __pa_symbol(secondary_startup);
 
 
        if (of_property_read_bool(np, "fsl,pmic-stby-poweroff"))
                imx6_pm_stby_poweroff_probe();
+
+       of_node_put(np);
 }
 
 void __init imx6q_pm_init(void)
 
 
        np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
        smc1_base = of_iomap(np, 0);
+       of_node_put(np);
        WARN_ON(!smc1_base);
 
        imx7ulp_set_lpm(ULP_PM_RUN);