powerpc/book3s/32: Use MMU_FTR_HPTE_TABLE in head_32.S

Instead of manually patching a blr at hash_page() entry in
MMU_init_hw(), this patch adds a features section in head_32.S

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 118c3b216e60c1e69c4597dc507d8cb12d9b68a4..15108b8caf6e868d4e56b01c1c65b4d7e5104486 100644 (file)
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -393,7 +393,9 @@ DataAccess:
        bne     1f                      /* if not, try to put a PTE */
        mfspr   r4,SPRN_DAR             /* into the hash table */
        rlwinm  r3,r10,32-15,21,21      /* DSISR_STORE -> _PAGE_RW */
+BEGIN_MMU_FTR_SECTION
        bl      hash_page
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
 1:     lwz     r5,_DSISR(r11)          /* get DSISR value */
        mfspr   r4,SPRN_DAR
        EXC_XFER_LITE(0x300, handle_page_fault)
@@ -408,7 +410,9 @@ InstructionAccess:
        beq     1f                      /* if so, try to put a PTE */
        li      r3,0                    /* into the hash table */
        mr      r4,r12                  /* SRR0 is fault address */
+BEGIN_MMU_FTR_SECTION
        bl      hash_page
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
 1:     mr      r4,r12
        andis.  r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
        EXC_XFER_LITE(0x400, handle_page_fault)

diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index f6f575bae3bceceae811b3cd54633f41d2633ecd..3c7c73defcb6ef29f7745fdb054b1f838147d607 100644 (file)
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -184,20 +184,10 @@ void __init MMU_init_hw(void)
 
        extern unsigned int hash_page_patch_A[];
        extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
-       extern unsigned int hash_page[];
        extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
 
-       if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
-               /*
-                * Put a blr (procedure return) instruction at the
-                * start of hash_page, since we can still get DSI
-                * exceptions on a 603.
-                */
-               hash_page[0] = 0x4e800020;
-               flush_icache_range((unsigned long) &hash_page[0],
-                                  (unsigned long) &hash_page[1]);
+       if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
                return;
-       }
 
        if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);