Merge tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel...

Pull RISC-V updates from Palmer Dabbelt:

 - The sub-architecture selection Kconfig system has been cleaned up,
   the documentation has been improved, and various detections have been
   fixed

 - The vector-related extensions dependencies are now validated when
   parsing from device tree and in the DT bindings

 - Misaligned access probing can be overridden via a kernel command-line
   parameter, along with various fixes to misalign access handling

 - Support for relocatable !MMU kernels builds

 - Support for hpge pfnmaps, which should improve TLB utilization

 - Support for runtime constants, which improves the d_hash()
   performance

 - Support for bfloat16, Zicbom, Zaamo, Zalrsc, Zicntr, Zihpm

 - Various fixes, including:
      - We were missing a secondary mmu notifier call when flushing the
        tlb which is required for IOMMU
      - Fix ftrace panics by saving the registers as expected by ftrace
      - Fix a couple of stimecmp usage related to cpu hotplug
      - purgatory_start is now aligned as per the STVEC requirements
      - A fix for hugetlb when calculating the size of non-present PTEs

* tag 'riscv-for-linus-6.15-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (65 commits)
  riscv: Add norvc after .option arch in runtime const
  riscv: Make sure toolchain supports zba before using zba instructions
  riscv/purgatory: 4B align purgatory_start
  riscv/kexec_file: Handle R_RISCV_64 in purgatory relocator
  selftests: riscv: fix v_exec_initval_nolibc.c
  riscv: Fix hugetlb retrieval of number of ptes in case of !present pte
  riscv: print hartid on bringup
  riscv: Add norvc after .option arch in runtime const
  riscv: Remove CONFIG_PAGE_OFFSET
  riscv: Support CONFIG_RELOCATABLE on riscv32
  asm-generic: Always define Elf_Rel and Elf_Rela
  riscv: Support CONFIG_RELOCATABLE on NOMMU
  riscv: Allow NOMMU kernels to access all of RAM
  riscv: Remove duplicate CONFIG_PAGE_OFFSET definition
  RISC-V: errata: Use medany for relocatable builds
  dt-bindings: riscv: document vector crypto requirements
  dt-bindings: riscv: add vector sub-extension dependencies
  dt-bindings: riscv: d requires f
  RISC-V: add f & d extension validation checks
  RISC-V: add vector crypto extension validation checks
  ...

diff --cc Documentation/admin-guide/kernel-parameters.txt
Simple merge

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/include/asm/bitops.h
Simple merge

diff --cc arch/riscv/kernel/sys_hwprobe.c
Simple merge

diff --cc arch/riscv/kvm/vcpu_onereg.c
Simple merge

diff --cc arch/riscv/mm/init.c
Simple merge

diff --cc arch/riscv/mm/tlbflush.c
index 74dd9307fbf1b4418b615e5f82afb81dd8a4f257,bb77607c87aa2d60c567b28e79dd884ac4c0b567..f9e27ba1df99ffeb5d4d450e933c15eb4aeeb92e
--- 1/arch/riscv/mm/tlbflush.c
--- 2/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@@ -186,9 -190,13 +190,10 @@@ bool arch_tlbbatch_should_defer(struct 
  }
  
  void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *batch,
 -                             struct mm_struct *mm,
 -                             unsigned long uaddr)
 +              struct mm_struct *mm, unsigned long start, unsigned long end)
  {
 -      unsigned long start = uaddr & PAGE_MASK;
 -
        cpumask_or(&batch->cpumask, &batch->cpumask, mm_cpumask(mm));
 -      mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, start + PAGE_SIZE);
++      mmu_notifier_arch_invalidate_secondary_tlbs(mm, start, end);
  }
  
  void arch_flush_tlb_batched_pending(struct mm_struct *mm)