drm/amd/display: fix dcn315 single stream crb allocation

Change to improve avoiding asymetric crb calculations for single stream
scenarios.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: Stylon Wang <stylon.wang@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index cb95e978417b6f8ca30a935e930bf14073a90801..8570bdc292b4f1a518ad81eef4fed991dceca7f5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1628,6 +1628,10 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context)
        int i;
        struct resource_context *res_ctx = &context->res_ctx;
 
+       /*Don't apply for single stream*/
+       if (context->stream_count < 2)
+               return false;
+
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
                if (!res_ctx->pipe_ctx[i].stream)
                        continue;
@@ -1727,19 +1731,23 @@ static int dcn315_populate_dml_pipes_from_context(
                pipe_cnt++;
        }
 
-       /* Spread remaining unreserved crb evenly among all pipes, use default policy if not enough det or single pipe */
+       /* Spread remaining unreserved crb evenly among all pipes*/
        if (pixel_rate_crb) {
                for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {
                        pipe = &res_ctx->pipe_ctx[i];
                        if (!pipe->stream)
                                continue;
 
+                       /* Do not use asymetric crb if not enough for pstate support */
+                       if (remaining_det_segs < 0) {
+                               pipes[pipe_cnt].pipe.src.det_size_override = 0;
+                               continue;
+                       }
+
                        if (!pipe->top_pipe && !pipe->prev_odm_pipe) {
                                bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)
                                                || (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);
 
-                               if (remaining_det_segs < 0 || crb_pipes == 1)
-                                       pipes[pipe_cnt].pipe.src.det_size_override = 0;
                                if (remaining_det_segs > MIN_RESERVED_DET_SEGS)
                                        pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +
                                                        (crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
@@ -1755,6 +1763,7 @@ static int dcn315_populate_dml_pipes_from_context(
                                }
                                /* Convert segments into size for DML use */
                                pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;
+
                                crb_idx++;
                        }
                        pipe_cnt++;