.resource       = pmu_resources,
 };
 
+static void __init ct_ca9x4_init_early(void)
+{
+       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+       v2m_init_early();
+}
+
 static void __init ct_ca9x4_init(void)
 {
        int i;
        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
-       clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
        for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
        .boot_params    = PHYS_OFFSET + 0x00000100,
        .map_io         = ct_ca9x4_map_io,
        .init_irq       = ct_ca9x4_init_irq,
+       .init_early     = ct_ca9x4_init_early,
 #if 0
        .timer          = &ct_ca9x4_timer,
 #else
 
        iotable_init(tile, num);
 }
 
+void __init v2m_init_early(void)
+{
+       versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
+}
 
 static void __init v2m_timer_init(void)
 {
        u32 scctrl;
 
-       versatile_sched_clock_init(MMIO_P2V(V2M_SYS_24MHZ), 24000000);
-
        /* Select 1MHz TIMCLK as the reference clock for SP804 timers */
        scctrl = readl(MMIO_P2V(V2M_SYSCTL + SCCTRL));
        scctrl |= SCCTRL_TIMEREN0SEL_TIMCLK;