irqchip/gic-v4.1: Avoid 64bit division for the sake of 32bit ARM

In order to allow the GICv4 code to link properly on 32bit ARM,
make sure we don't use 64bit divisions when it isn't strictly
necessary.

Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level")
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 1ee95f546cb0f3d7c809cded176beb1374001ab6..83b1186ffcad0d29893033019ab37fd478e4e180 100644 (file)
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2444,8 +2444,8 @@ static u64 inherit_vpe_l1_table_from_rd(cpumask_t **mask)
 static bool allocate_vpe_l2_table(int cpu, u32 id)
 {
        void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base;
-       u64 val, gpsz, npg;
-       unsigned int psz, esz, idx;
+       unsigned int psz, esz, idx, npg, gpsz;
+       u64 val;
        struct page *page;
        __le64 *table;