#define E1000_DEV_ID_PCH_CNP_I219_V6           0x15BE
 #define E1000_DEV_ID_PCH_CNP_I219_LM7          0x15BB
 #define E1000_DEV_ID_PCH_CNP_I219_V7           0x15BC
+#define E1000_DEV_ID_PCH_ICP_I219_LM8          0x15DF
+#define E1000_DEV_ID_PCH_ICP_I219_V8           0x15E0
+#define E1000_DEV_ID_PCH_ICP_I219_LM9          0x15E1
+#define E1000_DEV_ID_PCH_ICP_I219_V9           0x15E2
 
 #define E1000_REVISION_4       4
 
 
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
        { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM8), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V8), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_LM9), board_pch_cnp },
+       { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_ICP_I219_V9), board_pch_cnp },
 
        { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
 };