if (amdgpu_umc_pages_in_a_row(adev, err_data,
                                        bps[0].retired_page << AMDGPU_GPU_PAGE_SHIFT))
                                return -EINVAL;
+                       for (i = 0; i < adev->umc.retire_unit; i++) {
+                               err_data->err_addr[i].address = bps[0].address;
+                               err_data->err_addr[i].mem_channel = bps[0].mem_channel;
+                               err_data->err_addr[i].bank = bps[0].bank;
+                               err_data->err_addr[i].err_type = bps[0].err_type;
+                               err_data->err_addr[i].mcumc_id = bps[0].mcumc_id;
+                       }
                } else {
                        if (amdgpu_ras_mca2pa_by_idx(adev, &bps[0], err_data))
                                return -EINVAL;
                                struct eeprom_table_record *bps, struct ras_err_data *err_data,
                                enum amdgpu_memory_partition nps)
 {
+       int i = 0;
        enum amdgpu_memory_partition save_nps;
 
        save_nps = (bps->retired_page >> UMC_NPS_SHIFT) & UMC_NPS_MASK;
                if (amdgpu_umc_pages_in_a_row(adev, err_data,
                                bps->retired_page << AMDGPU_GPU_PAGE_SHIFT))
                        return -EINVAL;
+               for (i = 0; i < adev->umc.retire_unit; i++) {
+                       err_data->err_addr[i].address = bps->address;
+                       err_data->err_addr[i].mem_channel = bps->mem_channel;
+                       err_data->err_addr[i].bank = bps->bank;
+                       err_data->err_addr[i].err_type = bps->err_type;
+                       err_data->err_addr[i].mcumc_id = bps->mcumc_id;
+               }
        } else {
                if (bps->address) {
                        if (amdgpu_ras_mca2pa_by_idx(adev, bps, err_data))