value = readl_relaxed(ie) & ~mask;
        writel_relaxed(value, ie);
        raw_spin_unlock_irqrestore(&sfp->lock, flags);
+
+       gpiochip_disable_irq(&sfp->gc, d->hwirq);
 }
 
 static void starfive_irq_mask_ack(struct irq_data *d)
        unsigned long flags;
        u32 value;
 
+       gpiochip_enable_irq(&sfp->gc, d->hwirq);
+
        raw_spin_lock_irqsave(&sfp->lock, flags);
        value = readl_relaxed(ie) | mask;
        writel_relaxed(value, ie);
        return 0;
 }
 
-static struct irq_chip starfive_irq_chip = {
+static const struct irq_chip starfive_irq_chip = {
        .name = "StarFive GPIO",
        .irq_ack = starfive_irq_ack,
        .irq_mask = starfive_irq_mask,
        .irq_mask_ack = starfive_irq_mask_ack,
        .irq_unmask = starfive_irq_unmask,
        .irq_set_type = starfive_irq_set_type,
-       .flags = IRQCHIP_SET_TYPE_MASKED,
+       .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SET_TYPE_MASKED,
+       GPIOCHIP_IRQ_RESOURCE_HELPERS,
 };
 
 static void starfive_gpio_irq_handler(struct irq_desc *desc)
        sfp->gc.base = -1;
        sfp->gc.ngpio = NR_GPIOS;
 
-       sfp->gc.irq.chip = &starfive_irq_chip;
+       gpio_irq_chip_set_chip(&sfp->gc.irq, &starfive_irq_chip);
        sfp->gc.irq.parent_handler = starfive_gpio_irq_handler;
        sfp->gc.irq.num_parents = 1;
        sfp->gc.irq.parents = devm_kcalloc(dev, sfp->gc.irq.num_parents,