The PCIE Data Object Exchange (DOE) mailbox is a protocol run over
configuration cycles.  It assumes one initiator at a time.  While the
kernel has control of the mailbox user space writes could interfere with
the kernel access.
Mark DOE mailbox config space exclusive when iterated by the CXL driver.
Signed-off-by: Ira Weiny <ira.weiny@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20220926215711.2893286-3-ira.weiny@intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
                        continue;
                }
 
+               if (!pci_request_config_region_exclusive(pdev, off,
+                                                        PCI_DOE_CAP_SIZEOF,
+                                                        dev_name(dev)))
+                       pci_err(pdev, "Failed to exclude DOE registers\n");
+
                if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) {
                        dev_err(dev, "xa_insert failed to insert MB @ %x\n",
                                off);
 
 #define  PCI_DOE_STATUS_DATA_OBJECT_READY      0x80000000  /* Data Object Ready */
 #define PCI_DOE_WRITE          0x10    /* DOE Write Data Mailbox Register */
 #define PCI_DOE_READ           0x14    /* DOE Read Data Mailbox Register */
+#define PCI_DOE_CAP_SIZEOF     0x18    /* Size of DOE register block */
 
 /* DOE Data Object - note not actually registers */
 #define PCI_DOE_DATA_OBJECT_HEADER_1_VID               0x0000ffff