memory: tegra: Replace readl-writel with mc_readl-mc_writel

There is no need for a memory barriers on reading/writing of register
values as we only care about the read/write order, hence let's use the
common helpers.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 483ac3c1a762a07b738b43b7464152e0103de17c..163b6c69e65193a5ed75028f85a53d3a5a90c813 100644 (file)
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -288,24 +288,24 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
        tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
        do_div(tick, NSEC_PER_SEC);
 
-       value = readl(mc->regs + MC_EMEM_ARB_CFG);
+       value = mc_readl(mc, MC_EMEM_ARB_CFG);
        value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
        value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
-       writel(value, mc->regs + MC_EMEM_ARB_CFG);
+       mc_writel(mc, value, MC_EMEM_ARB_CFG);
 
        /* write latency allowance defaults */
        for (i = 0; i < mc->soc->num_clients; i++) {
                const struct tegra_mc_la *la = &mc->soc->clients[i].la;
                u32 value;
 
-               value = readl(mc->regs + la->reg);
+               value = mc_readl(mc, la->reg);
                value &= ~(la->mask << la->shift);
                value |= (la->def & la->mask) << la->shift;
-               writel(value, mc->regs + la->reg);
+               mc_writel(mc, value, la->reg);
        }
 
        /* latch new values */
-       writel(MC_TIMING_UPDATE, mc->regs + MC_TIMING_CONTROL);
+       mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
 
        return 0;
 }