arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM

Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
interface with the Type-C port via the USB hub, by configuring the pin P05
of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
mode of operation with Lane 0 of the SERDES0 instance of SERDES.

Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20240615081600.3602462-8-s-vadapalli@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1f5fc09f72427a2aa84fdf0ef16c1..253b02f0437de3397af6f698eb1cc4c0a0c38432 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
 #include "k3-j722s.dtsi"
+#include "k3-serdes.h"
 
 / {
        compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@
                        J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
                >;
        };
+
+       main_usb1_pins_default: main-usb1-default-pins {
+               pinctrl-single,pins = <
+                       J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+               >;
+       };
 };
 
 &cpsw3g {
@@ -301,6 +309,13 @@
                                  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
                                  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
                                  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+               p05-hog {
+                       /* P05 - USB2.0_MUX_SEL */
+                       gpio-hog;
+                       gpios = <5 GPIO_ACTIVE_HIGH>;
+                       output-high;
+               };
        };
 };
 
@@ -384,3 +399,61 @@
        status = "okay";
        bootph-all;
 };
+
+&serdes_ln_ctrl {
+       idle-states = <J722S_SERDES0_LANE0_USB>,
+                     <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+       status = "okay";
+       serdes0_usb_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_USB3>;
+               resets = <&serdes_wiz0 1>;
+       };
+};
+
+&serdes1 {
+       status = "okay";
+       serdes1_pcie_link: phy@0 {
+               reg = <0>;
+               cdns,num-lanes = <1>;
+               #phy-cells = <0>;
+               cdns,phy-type = <PHY_TYPE_PCIE>;
+               resets = <&serdes_wiz1 1>;
+       };
+};
+
+&pcie0_rc {
+       reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+       phys = <&serdes1_pcie_link>;
+       phy-names = "pcie-phy";
+       status = "okay";
+};
+
+&usbss0 {
+       ti,vbus-divider;
+       status = "okay";
+};
+
+&usb0 {
+       dr_mode = "otg";
+       usb-role-switch;
+};
+
+&usbss1 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&main_usb1_pins_default>;
+       ti,vbus-divider;
+       status = "okay";
+};
+
+&usb1 {
+       dr_mode = "host";
+       maximum-speed = "super-speed";
+       phys = <&serdes0_usb_link>;
+       phy-names = "cdns3,usb3-phy";
+};