serial: 8250_mid: handle interrupt correctly in DMA case

Starting from Tangier B0 and continuing on Anniedale the HSU DMA interrupt
line is actually shared with UART. Handling them independently is racy and
quite often comes with the following traceback.

 irq 54: nobody cared (try booting with the "irqpoll" option)
 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.9.0-rc6-edison64-86244934+ #1
 Hardware name: Intel Corporation Merrifield/BODEGA BAY, BIOS 542 2015.01.21:18.19.48
  ffff88003f203eb0 ffffffff8130e718 ffff880032627000 ffff88003262709c
  ffff88003f203ed8 ffffffff810a3960 ffff880032627000 0000000000000000
  ffff880032627000 ffff88003f203f10 ffffffff810a3cc7 ffff880032627000
 Call Trace:
  <IRQ>
  [<ffffffff8130e718>] dump_stack+0x4d/0x65
  [<ffffffff810a3960>] __report_bad_irq+0x30/0xc0
  [<ffffffff810a3cc7>] note_interrupt+0x227/0x270
  [<ffffffff810a1380>] handle_irq_event_percpu+0x40/0x50
  [<ffffffff810a13b7>] handle_irq_event+0x27/0x50
  [<ffffffff810a42d5>] handle_fasteoi_irq+0x85/0x150
  [<ffffffff8101d7fe>] handle_irq+0x6e/0x120
  [<ffffffff8105b8bc>] ? _local_bh_enable+0x1c/0x50
  [<ffffffff8101d0d6>] do_IRQ+0x46/0xd0
  [<ffffffff818cef3f>] common_interrupt+0x7f/0x7f
  <EOI>
  [<ffffffff818cdead>] ? mwait_idle+0x7d/0x140
  [<ffffffff81024c9a>] arch_cpu_idle+0xa/0x10
  [<ffffffff818ce150>] default_idle_call+0x20/0x30
  [<ffffffff810908fd>] cpu_startup_entry+0x16d/0x1d0
  [<ffffffff818c882d>] rest_init+0x6d/0x70
  [<ffffffff81f93e8f>] start_kernel+0x3e2/0x3ef
  [<ffffffff81f9343d>] x86_64_start_reservations+0x38/0x3a
  [<ffffffff81f93529>] x86_64_start_kernel+0xea/0xed
 handlers:
 [<ffffffff81411670>] serial8250_interrupt
 Disabling IRQ #54

Fix this by handling interrupt only in one place.

The issue is discussed here: https://github.com/andy-shev/linux/issues/5

Moreover this also fixes another bug when Rx DMA returns wrong residue and we
can't rely on it.

Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/dma/hsu/pci.c b/drivers/dma/hsu/pci.c
index 4875fa428e813e07d36c82a86a41c4a3e9d5c82e..ad45cd344bbaeca6a183aacce71585bafde4af20 100644 (file)
--- a/drivers/dma/hsu/pci.c
+++ b/drivers/dma/hsu/pci.c
@@ -23,15 +23,28 @@
 
 #define HSU_PCI_CHAN_OFFSET    0x100
 
+#define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA       0x081e
+#define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA      0x1192
+
 static irqreturn_t hsu_pci_irq(int irq, void *dev)
 {
        struct hsu_dma_chip *chip = dev;
+       struct pci_dev *pdev = to_pci_dev(chip->dev);
        u32 dmaisr;
        u32 status;
        unsigned short i;
        int ret = 0;
        int err;
 
+       /*
+        * On Intel Tangier B0 and Anniedale the interrupt line, disregarding
+        * to have different numbers, is shared between HSU DMA and UART IPs.
+        * Thus on such SoCs we are expecting that IRQ handler is called in
+        * UART driver only.
+        */
+       if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
+               return IRQ_HANDLED;
+
        dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
        for (i = 0; i < chip->hsu->nr_channels; i++) {
                if (dmaisr & 0x1) {
@@ -113,8 +126,8 @@ static void hsu_pci_remove(struct pci_dev *pdev)
 }
 
 static const struct pci_device_id hsu_pci_id_table[] = {
-       { PCI_VDEVICE(INTEL, 0x081e), 0 },
-       { PCI_VDEVICE(INTEL, 0x1192), 0 },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
+       { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
        { }
 };
 MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);

diff --git a/drivers/tty/serial/8250/8250_mid.c b/drivers/tty/serial/8250/8250_mid.c
index ac013edf4992e74362f62ba34789f57b63ba9128..6730d9eef81e7365c9473b459522b03ce6be51e5 100644 (file)
--- a/drivers/tty/serial/8250/8250_mid.c
+++ b/drivers/tty/serial/8250/8250_mid.c
@@ -75,6 +75,37 @@ static int pnw_setup(struct mid8250 *mid, struct uart_port *p)
        return 0;
 }
 
+static int tng_handle_irq(struct uart_port *p)
+{
+       struct mid8250 *mid = p->private_data;
+       struct uart_8250_port *up = up_to_u8250p(p);
+       struct hsu_dma_chip *chip;
+       u32 status;
+       int ret = 0;
+       int err;
+
+       chip = pci_get_drvdata(mid->dma_dev);
+
+       /* Rx DMA */
+       err = hsu_dma_get_status(chip, mid->dma_index * 2 + 1, &status);
+       if (err > 0) {
+               serial8250_rx_dma_flush(up);
+               ret |= 1;
+       } else if (err == 0)
+               ret |= hsu_dma_do_irq(chip, mid->dma_index * 2 + 1, status);
+
+       /* Tx DMA */
+       err = hsu_dma_get_status(chip, mid->dma_index * 2, &status);
+       if (err > 0)
+               ret |= 1;
+       else if (err == 0)
+               ret |= hsu_dma_do_irq(chip, mid->dma_index * 2, status);
+
+       /* UART */
+       ret |= serial8250_handle_irq(p, serial_port_in(p, UART_IIR));
+       return IRQ_RETVAL(ret);
+}
+
 static int tng_setup(struct mid8250 *mid, struct uart_port *p)
 {
        struct pci_dev *pdev = to_pci_dev(p->dev);
@@ -90,6 +121,8 @@ static int tng_setup(struct mid8250 *mid, struct uart_port *p)
 
        mid->dma_index = index;
        mid->dma_dev = pci_get_slot(pdev->bus, PCI_DEVFN(5, 0));
+
+       p->handle_irq = tng_handle_irq;
        return 0;
 }