aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sc7180-aoss-qmp";
-                       reg = <0 0x0c300000 0 0x100000>;
+                       reg = <0 0x0c300000 0 0x400>;
                        interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
                        mboxes = <&apss_shared 0>;
 
                        #clock-cells = <0>;
                };
 
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
+               };
+
                spmi_bus: spmi@c440000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0 0x0c440000 0 0x1100>,
 
 
                aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sc7280-aoss-qmp";
-                       reg = <0 0x0c300000 0 0x100000>;
+                       reg = <0 0x0c300000 0 0x400>;
                        interrupts-extended = <&ipcc IPCC_CLIENT_AOP
                                                     IPCC_MPROC_SIGNAL_GLINK_QMP
                                                     IRQ_TYPE_EDGE_RISING>;
                        #clock-cells = <0>;
                };
 
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
+               };
+
                spmi_bus: spmi@c440000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0 0x0c440000 0 0x1100>,
 
 
                aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sm8150-aoss-qmp";
-                       reg = <0x0 0x0c300000 0x0 0x100000>;
+                       reg = <0x0 0x0c300000 0x0 0x400>;
                        interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
                        mboxes = <&apss_shared 0>;
 
                        #clock-cells = <0>;
                };
 
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
+               };
+
                tsens0: thermal-sensor@c263000 {
                        compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
                        reg = <0 0x0c263000 0 0x1ff>, /* TM */
 
 
                aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sm8250-aoss-qmp";
-                       reg = <0 0x0c300000 0 0x100000>;
+                       reg = <0 0x0c300000 0 0x400>;
                        interrupts-extended = <&ipcc IPCC_CLIENT_AOP
                                                     IPCC_MPROC_SIGNAL_GLINK_QMP
                                                     IRQ_TYPE_EDGE_RISING>;
                        #clock-cells = <0>;
                };
 
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
+               };
+
                spmi_bus: spmi@c440000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0x0 0x0c440000 0x0 0x0001100>,
 
 
                aoss_qmp: power-controller@c300000 {
                        compatible = "qcom,sm8350-aoss-qmp";
-                       reg = <0 0x0c300000 0 0x100000>;
+                       reg = <0 0x0c300000 0 0x400>;
                        interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
                                                     IRQ_TYPE_EDGE_RISING>;
                        mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
                        #clock-cells = <0>;
                };
 
+               sram@c3f0000 {
+                       compatible = "qcom,rpmh-stats";
+                       reg = <0 0x0c3f0000 0 0x400>;
+               };
+
                spmi_bus: spmi@c440000 {
                        compatible = "qcom,spmi-pmic-arb";
                        reg = <0x0 0xc440000 0x0 0x1100>,