Only needed when CONFIG_BOOTDELAY is enabled;
define a command string that is automatically executed
when no character is read on the console interface
- withing "Boot Delay" after reset.
+ within "Boot Delay" after reset.
CONFIG_BOOTARGS
This can be used to pass arguments to the bootm command.
of the backslashes before semicolons and special
symbols.
+- Default Environment
+ CONFIG_EXTRA_ENV_SETTINGS
+
+ Define this to contain any number of null terminated
+ strings (variable = value pairs) that will be part of
+ the default enviroment compiled into the boot image.
+ For example, place something like this in your
+ board's config file:
+
+ #define CONFIG_EXTRA_ENV_SETTINGS \
+ "myvar1=value1\0" \
+ "myvar2=value2\0"
+
+ Warning: This method is based on knowledge about the
+ internal format how the environment is stored by the
+ PPCBoot code. This is NOT an official, expoerted
+ interface! Although it is unlikely that this format
+ will change soon, there is no guarantee either.
+ You better know what you are doing here.
+
+ Note: overly (ab)use of the default environment is
+ discouraged. Make sure to check other ways to preset
+ the environment like the autoscript function or the
+ boot command first.
+
Configuration Settings:
-----------------------
*/
const uint sdram_table[] =
{
+#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)
/*
* Single Read. (Offset 0 in UPM RAM)
*/
*/
0x7FFFFC07, /* last */
0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
+#ifdef CFG_MEMORY_7E
+ /*
+ * Single Read. (Offset 0 in UPM RAM)
+ */
+ 0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
+ _NOT_USED_,
+ /*
+ * SDRAM Initialization (offset 5 in UPM RAM)
+ *
+ * This is no UPM entry point. The following definition uses
+ * the remaining space to establish an initialization
+ * sequence, which is executed by a RUN command.
+ *
+ */
+ 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
+ /*
+ * Burst Read. (Offset 8 in UPM RAM)
+ */
+ 0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
+ 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Single Write. (Offset 18 in UPM RAM)
+ */
+ 0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
+ _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Burst Write. (Offset 20 in UPM RAM)
+ */
+ 0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
+ 0xE1BAFC04, 0x1FF5FC47, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Refresh (Offset 30 in UPM RAM)
+ */
+ 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
+ 0xFFFFFC84, 0xFFFFFC07, /* last */
+ _NOT_USED_, _NOT_USED_,
+ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
+ /*
+ * Exception. (Offset 3c in UPM RAM)
+ */
+ 0x7FFFFC07, /* last */
+ 0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
+#endif
};
/* ------------------------------------------------------------------------- */
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immr->im_memctl;
long int size_b0;
+ long int size8, size9;
int i;
/*
memctl->memc_mptpr = CFG_MPTPR;
/* burst length=4, burst type=sequential, CAS latency=2 */
- memctl->memc_mar = 0x00000088;
+ memctl->memc_mar = CFG_MAR;
/*
* Map controller bank 3 to the SDRAM bank at preliminary address.
memctl->memc_br3 = CFG_BR3_PRELIM;
/* initialize memory address register */
- memctl->memc_mamr = CFG_MAMR; /* refresh not enabled yet */
+ memctl->memc_mamr = CFG_MAMR_8COL; /* refresh not enabled yet */
/* mode initialization (offset 5) */
udelay(200); /* 0x80006105 */
/*
* Check Bank 0 Memory Size for re-configuration
+ *
+ * try 8 column mode
*/
- size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+ size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ udelay (1000);
- memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
+ /*
+ * try 9 column mode
+ */
+ size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+
+ if (size8 < size9) { /* leave configuration at 9 columns */
+ size_b0 = size9;
+ memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
+ udelay(500);
+ } else { /* back to 8 columns */
+ size_b0 = size8;
+ memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
+ udelay(500);
+ }
/*
* Final mapping: